Commit Graph

248058 Commits

Author SHA1 Message Date
Marcin Koscielnicki 9a063e7c02 [CodeGen] Insert TargetLibraryInfoWrapperPass before anything else.
Currently, TargetLibraryInfoWrapperPass is inserted by PMBuilder.
However, some passes are inserted manually before the PMBuilder
ones - if any of them happens to use TargetLibraryInfoWrapperPass,
it'll get a default-constructed one, with an unknown target triple.
This happens to InstrProfiling in D21736, breaking it.

Differential Revision: http://reviews.llvm.org/D21737

llvm-svn: 287688
2016-11-22 20:03:35 +00:00
Eric Fiselier 3028189ee3 Cleanup module.modulemap
llvm-svn: 287687
2016-11-22 20:00:21 +00:00
Paul Robinson f428c9b298 Restructure DwarfDebug::beginInstruction(). [NFC]
Will help a pending patch.

Differential Revision: http://reviews.llvm.org/D26982

llvm-svn: 287686
2016-11-22 19:46:51 +00:00
Nico Weber 9b3baaa74a darwin: Unconditionally pass -lto_library, remove -Wliblto warning.
https://reviews.llvm.org/D25932 made it so that clang always checks if
libLTO.dylib is present on disk, even if -flto is not being used. The
motivation for that change was that if a dependency happens to contain bitcode,
ld64 will try to load libLTO without -flto explicitly being enabled. However,
the change had the undesirable side effect of warning if libLTO.dylib doesn't
exist even if it isn't needed.

Change things so that -lto_library is always passes, independent of if it
exists or not. ld64 only looks at this flag if it uses LTO. If the dylib
exists, all is well. If it doesn't, and LTO is not being used, all is well too.
If ld64 does end up using LTO and the dylib does not exist, ld64 will print
something like

    ld: could not process llvm bitcode object file, because foo/libLTO.dylib could not be loaded file 'test.o' for architecture x86_64

https://reviews.llvm.org/D26984

llvm-svn: 287685
2016-11-22 19:38:07 +00:00
Shoaib Meenai 5497121613 [Triple] Add Facebook vendor
Add a compiler vendor for Facebook, to enable future vendor-specific
behavior.

Differential Revision: https://reviews.llvm.org/D25136

llvm-svn: 287684
2016-11-22 19:36:26 +00:00
Rui Ueyama bdfa155fa2 Fix build breakage.
We cannot have MipsRldMap class and In<ELFT>::MipsRldMap.
Renamed the class.

llvm-svn: 287683
2016-11-22 19:24:52 +00:00
Chandler Carruth bae595b742 [LCG] Add utilities to compute parent and ascestor relationships between
SCCs.

These will be fairly expensive routines to call and might be abused in
real code, but are quite useful when debugging or in asserts and are
reasonable and well formed properties to query.

I've used one of them in an assert that was requested in a code review
here. In subsequent commits I'll start using these routines more
heavily, for example in unittests etc. But this at least gets the
groundwork in place.

Differential Revision: https://reviews.llvm.org/D25506

llvm-svn: 287682
2016-11-22 19:23:31 +00:00
Simon Dardis 6efb8dd2e3 [mips] seb, seh instruction aliases
Add the single operand form.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D26961

llvm-svn: 287681
2016-11-22 19:17:23 +00:00
Andrew Kaylor 57d35bf7e1 Add IntrInaccessibleMemOnly property for intrinsics
Differential Revision: https://reviews.llvm.org/D26485

llvm-svn: 287680
2016-11-22 19:16:04 +00:00
Nemanja Ivanovic b8e30d6db6 [PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE
This patch corresponds to review:
https://reviews.llvm.org/D26861

It also fixes PR30730.

Committing on behalf of Lei Huang.

llvm-svn: 287679
2016-11-22 19:02:07 +00:00
Simon Pilgrim d1aed9a9e6 [CostModel][X86] Updated sitofp/uitofp scalar/vector cost tests
Better coverage of all legal types + special cases.

Removed old fptoui tests which are all handled in fptoui.ll

llvm-svn: 287678
2016-11-22 18:55:49 +00:00
Meador Inge b2d99d6a0f [ELF] Allow `ASSERT` in output section descriptions
GNU LD allows `ASSERT` commands to be in output section descriptions.
Note that LD also mandates that `ASSERT` commands in this context must
end with a semicolon.

llvm-svn: 287677
2016-11-22 18:01:50 +00:00
Simon Pilgrim 4aa876ca7c [X86][SSE] Combine UNPCKL(FHADD,FHADD) -> FHADD for v2f64 shuffles.
This occurs during UINT_TO_FP v2f64 lowering. 

We can easily generalize this to other horizontal ops (FHSUB, PACKSS, PACKUS) as required - we are doing something similar with PACKUS in lowerV2I64VectorShuffle

llvm-svn: 287676
2016-11-22 17:50:06 +00:00
Eugene Leviant 17b7a57533 [ELF] Convert .rld_map to input section
Differential revision: https://reviews.llvm.org/D26958

llvm-svn: 287675
2016-11-22 17:49:14 +00:00
Benjamin Kramer b568d99dd7 [clang-rename] Prune away AST nodes more correctly and effectively when looking for a point
Due to the way the preprocessor works nodes can be half in a macro or a
different file. This means checking the file name of the start location
of a Decl is not a correct way of checking if the entire Decl is in that
file. Remove that flawed assumption and replace it with a more effective
check: If the point we're looking for is *inside* of the begin and end
location of a Decl, look inside.

This should make clang-rename more reliable (for example macro'd namespaces
threw it off before, as seen in the test case) and maybe a little faster
by pruning off more stuff that the RecursiveASTVisitor doesn't have to
drill into.

llvm-svn: 287649
2016-11-22 17:29:45 +00:00
Zachary Turner d6a2475787 Re-add "demonstrate new Args API"
This fixes the build breakage due to the use of C++14.

llvm-svn: 287647
2016-11-22 17:10:15 +00:00
Vasileios Kalintiris 04dc211e6a [mips] Add support for unaligned load/store macros.
Add missing unaligned store macros (ush/usw) and fix the exisiting
implementation of the unaligned load macros in order to generate
identical expansions with the GNU assembler.

llvm-svn: 287646
2016-11-22 16:43:49 +00:00
Tim Northover b64fb453ea CodeGen: simplify TargetMachine::getSymbol interface. NFC.
No-one actually had a mangler handy when calling this function, and
getSymbol itself went most of the way towards getting its own mangler
(with a local TLOF variable) so forcing all callers to supply one was
just extra complication.

llvm-svn: 287645
2016-11-22 16:17:20 +00:00
Zvi Rackover 9a355219d1 [X86] Change lowerBuildVectorToBitOp() to take a BuildVectorSDNode. NFC.
llvm-svn: 287644
2016-11-22 15:33:28 +00:00
Zvi Rackover 0aa1c32d14 [X86] Remove dead code from LowerVectorBroadcast
Summary: Splat vectors are canonicalized to BUILD_VECTOR's so the code can be simplified. NFC-ish.

Reviewers: craig.topper, delena, RKSimon, andreadb

Subscribers: RKSimon, llvm-commits

Differential Revision: https://reviews.llvm.org/D26678

llvm-svn: 287643
2016-11-22 15:17:52 +00:00
Chad Rosier ecc77273a0 [AArch64] Set the max interleave factor for Falkor.
llvm-svn: 287642
2016-11-22 14:25:02 +00:00
Chad Rosier 2abc29c593 [AArch64] Maximize 80-column. NFC.
llvm-svn: 287640
2016-11-22 14:12:09 +00:00
Eric Liu e86a5f4c65 Make llvm::Error generated from replacement interfaces more specific.
Summary:
The new error information contains the type of error (e.g. overlap or bad file path)
and the replacement(s) that is causing the error. This enables us to resolve some errors.
For example, for insertion at the same location conflict, we need to know the
existing replacement which conflicts with the new replacement in order to calculate
the new position to be insert before/after the existing replacement (for merging).

Reviewers: klimek, bkramer

Subscribers: djasper, cfe-commits

Differential Revision: https://reviews.llvm.org/D26853

llvm-svn: 287639
2016-11-22 13:46:42 +00:00
Simon Pilgrim d70c03ad68 Fix line endings
llvm-svn: 287638
2016-11-22 13:27:29 +00:00
Benjamin Kramer ee8c585d04 [wasm] hack around test failure after r287553.
This test is very brittle as small changes to block layout break the
check patterns. Hack around a change one more time.

llvm-svn: 287637
2016-11-22 13:13:33 +00:00
Sam McCall 30621391bc Improve detection of global vs local variables
Summary:
Improve detection of global vs local variables.

Currently when a global variable is optimized out or otherwise has an unknown
location (DW_AT_location is empty) it gets reported as local.

I added two new heuristics:
 - if a mangled name is present, the variable is global (or static)
 - if DW_AT_location is present but invalid, the variable is global (or static)

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D26908

llvm-svn: 287636
2016-11-22 11:40:25 +00:00
Simon Pilgrim 72e43570b7 [SelectionDAG] ComputeNumSignBits of TRUNCATE operations
Add basic ComputeNumSignBits support for TRUNCATE ops for cases where the source's number of sign bits overlaps with the truncated size.

Improves X86 SIGN_EXTEND_IN_REG vector cases which were needlessly sign extending boolean vector results.

Differential Revision: https://reviews.llvm.org/D26851

llvm-svn: 287635
2016-11-22 11:29:19 +00:00
Dmitry Vyukov 9c5bab23ee tsan: fix build after 287632
1. Mac does not have MAP_32BIT.
Define it to 0 if it is not defined.

2. We are lacking nolibc stub for ListOfModules::init.
Add it.

llvm-svn: 287634
2016-11-22 11:09:35 +00:00
Axel Naumann b920aa0fae Missing initializer.
llvm-svn: 287633
2016-11-22 10:00:23 +00:00
Dmitry Vyukov 5c5d4766f8 tsan: switch libignore from /proc/self/maps to dl_iterate_phdr
/proc/self/maps can't be read atomically, this leads to episodic
crashes in libignore as it thinks that a module is loaded twice.
See the new test for an example.
dl_iterate_phdr does not have this problem.
Switch libignore to dl_iterate_phdr.

llvm-svn: 287632
2016-11-22 09:49:11 +00:00
Omair Javaid 99a318e112 Fix build failure on Linux and BSD by reverting r287597
Linux and BSD builds failing after this changes from rev 287597.

llvm-svn: 287631
2016-11-22 09:47:00 +00:00
Coby Tayree 49b3733d57 [AVX512][inline-asm] Fix AVX512 inline assembly instruction resolution when the size qualifier of a memory operand is not specified explicitly.
This commit handles cases where the size qualifier of an indirect memory reference operand in Intel syntax is missing (e.g. "vaddps xmm1, xmm2, [a]").

GCC will deduce the size qualifier for AVX512 vector and broadcast memory operands based on the possible matches:
"vaddps xmm1, xmm2, [a]" matches only “XMMWORD PTR” qualifier.
"vaddps xmm1, xmm2, [a]{1to4}" matches only “DWORD PTR” qualifier.

This is different from the current behavior of LLVM, which deduces the size qualifier based on the size of the memory operand.
For "vaddps xmm1, xmm2, [a]"
"char a;" will imply "BYTE PTR" qualifier
"short a;" will imply "WORD PTR" qualifier.

This commit aligns LLVM to GCC’s behavior.

This is the LLVM part of the review.
The Clang part of the review: https://reviews.llvm.org/D26587

Differential Revision: https://reviews.llvm.org/D26586

llvm-svn: 287630
2016-11-22 09:30:29 +00:00
Dmitry Vyukov 8b2ddfeb0b tsan: mark cur_thread_placeholder definition as initial-exec
See https://sourceware.org/bugzilla/show_bug.cgi?id=20805 and
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78294 for context.
Previously we marked only declaration as initial-exec. But compilers treat
initial-exec attribute somewhat differently. Mark definition as well.

llvm-svn: 287629
2016-11-22 08:59:17 +00:00
Adam Nemet 43018fdbe5 Rename option to -lto-pass-remarks-output
The new option -pass-remarks-output broke LLVM_LINK_LLVM_DYLIB because
of the duplicate option name with opt.

llvm-svn: 287628
2016-11-22 07:35:19 +00:00
Adam Nemet de33651bd9 Rename option to -lto-pass-remarks-output
The new option -pass-remarks-output broke LLVM_LINK_LLVM_DYLIB because
of the duplicate option name with opt.

llvm-svn: 287627
2016-11-22 07:35:14 +00:00
Tobias Grosser d51a945f38 [test] Simplify test case by removing unreferenced instructions [NFC]
Drop instructions that do not influence the memory impact of a basic block.
They are not needed to reproduce the original bug (verified) and will cause
random test noise if we would decide to only model the instructions that
have visible side-effects.

llvm-svn: 287626
2016-11-22 07:18:57 +00:00
Tobias Grosser 88c025e82e [test] Ensure important basic blocks in test case have side effects
Add two store instructions at the end of basic blocks that are required to
reproduce the original bug to ensure we always process and model these basic
blocks. This makes this test case stable even in case we would decide to bail
out early of basic blocks which do not modify the global state. Also add
additional check lines to verify how we model the basic block.

llvm-svn: 287625
2016-11-22 07:06:59 +00:00
Craig Topper 3dc066754c [TableGen][ISel] When factoring ScopeMatcher, if the child of the ScopeMatcher we're working on is also a ScopeMatcher, merge all its children into the one we're working on.
There were several cases in X86 where we were unable to fully factor a ScopeMatcher but created nested ScopeMatchers for some portions of it. Then we created a SwitchType that split it up and further factored it so that we ended up with something like this:

SwitchType
  Scope
    Scope
      Sequence of matchers
      Some other sequence of matchers
    EndScope
    Another sequence of matchers
  EndScope
...Next type

This change turns it into this:

SwitchType
  Scope
    Sequence of matchers
    Some other sequence of matchers
    Another sequence of matchers
  EndScope
...Next type

Several other in-tree targets had similar nested scopes like this. Overall this doesn't save many bytes, but makes the isel output a little more regular.

llvm-svn: 287624
2016-11-22 07:00:06 +00:00
Tobias Grosser 07ce9a0bcc test: add more details to non-affine test case
We add CHECK lines to this test case to make it easier to see the difference
between affine and non-affine memory accesses. We also change the test case to
use a parameteric index expression as otherwise our range analysis will
understand that the non-affine memory access can only access input[1],
which makes it difficult to see that the memory access is in-fact modeled as
non-affine access.

llvm-svn: 287623
2016-11-22 06:28:08 +00:00
Craig Topper 3dcf45f08d [X86] Remove alternate CodeGenOnly version of (v)movq that declared the load size as i128mem. Change all uses to the use the i64mem version.
I'm sure this caused the load size to misprint in Intel syntax output. We were also inconsistent about which patterns used which instruction between VEX and EVEX.

There are two different reg/reg versions of movq, one from a GPR and one from the lower 64-bits of an XMM register. This changes the loading folding table to use the single i64mem memory form for folding both cases. But we need to use TB_NO_REVERSE to prevent a duplicate entry in the unfolding table.

llvm-svn: 287622
2016-11-22 05:31:43 +00:00
Craig Topper cada9f2275 [AVX-512] Add support for commuting VPERMT2(B/W/D/Q/PS/PD) to/from VPERMI2(B/W/D/Q/PS/PD).
Summary:
The index and one of the table operands can be swapped by changing the opcode to the other version. Neither of these operands are the one that can load from memory so this can't be used to increase memory folding opportunities.

We need to handle the unmasked forms and the kz forms. Since the load operand isn't being commuted we can commute the load and broadcast instructions too.

Reviewers: igorb, delena, Ayal, Farhana, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25652

llvm-svn: 287621
2016-11-22 04:57:34 +00:00
Rui Ueyama 81a4b26b48 Inline small function. NFC.
llvm-svn: 287620
2016-11-22 04:33:01 +00:00
Saleem Abdulrasool 9b106ea072 MC: ensure that we have a section before accessing it
We would attempt to access the symbol section without ensuring that the symbol
was not absolute.  When the assembler referenced relocation is not evaluated to
the absolute, but when we record the relocation, we would query the section.
Because the symbol is absolute, it does not have a section associated with it,
triggering an assertion.  Just be more careful about the access of the section.

Addresses PR31064!

llvm-svn: 287619
2016-11-22 04:32:54 +00:00
Artem Dergachev 22e28f4078 [analyzer] Fix a crash on accessing a field within a literal-initialized union.
Because in case of unions we currently default-bind compound values in the
store, this quick fix avoids the crash for this case.

Patch by Ilya Palachev and independently by Alexander Shaposhnikov!

Differential Revision: https://reviews.llvm.org/D26442

llvm-svn: 287618
2016-11-22 04:29:23 +00:00
Rui Ueyama 1d75de00e8 Do not save unused pointers to In<ELFT>.
llvm-svn: 287617
2016-11-22 04:28:39 +00:00
Rui Ueyama 8b493f1ac6 Remove default definition no one uses.
llvm-svn: 287616
2016-11-22 04:17:12 +00:00
Rui Ueyama 9cfac8a849 Convert MipsOptionsSection to SyntheticSection.
llvm-svn: 287615
2016-11-22 04:13:09 +00:00
Rui Ueyama b71cae90de Convert MipsReginfoSection to SyntheticSection.
llvm-svn: 287614
2016-11-22 03:57:08 +00:00
Rui Ueyama 12f2da870e Convert MipsAbiFlagsSection to SyntheticSection.
llvm-svn: 287613
2016-11-22 03:57:06 +00:00
Craig Topper da22267055 [AVX-512] Add support for changing the element size of PALIGNR/VALIGND/VALIGNQ shuffles if they feed a vselect with a different type
Summary:
Shuffle lowering widens the element size of a shuffle if elements are contiguous. This is sometimes help because wider element types have more shuffle options. If the shuffle is one of the arguments to a vselect this shuffle widening can introduce a bitcast between the vselect and the shuffle. This will prevent isel from selecting a masked operation. If the shuffle can be written equally efficiently with a different element size to match the vselect type we should change the shuffle type to allow masking.

This patch does this conversion for all VALIGND/VALIGNQ sizes. It also supports turning 128-bit PALIGNR into VALIGND/VALIGNQ. This fixes the case shown in PR31018.

I plan to add support for more operations in future patches.

Reviewers: RKSimon, zvi, delena

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D26902

llvm-svn: 287612
2016-11-22 03:51:53 +00:00