Commit Graph

300298 Commits

Author SHA1 Message Date
Jan Kratochvil 0e99f561e1 Fix buildbot regression by rL339929: NameError: global name 'test_directory' is not defined
With buildbot slave under test - I get after rL339929:
http://lab.llvm.org:8014/builders/lldb-x86_64-fedora-28-cmake/builds/243/steps/test1/logs/stdio

  File "/home/buildbot/lldbroot/lldb-x86_64-fedora-28-cmake/scripts/../llvm/tools/lldb/test/dotest.py", line 7, in <module>
    lldbsuite.test.run_suite()
  File "/quad/home/buildbot/lldbroot/lldb-x86_64-fedora-28-cmake/llvm/tools/lldb/packages/Python/lldbsuite/test/dotest.py", line 1177, in run_suite
    configuration.results_formatter_object)
  File "/quad/home/buildbot/lldbroot/lldb-x86_64-fedora-28-cmake/llvm/tools/lldb/packages/Python/lldbsuite/test/dosep.py", line 1692, in main
    dst = core.replace(test_directory, "")[1:]
NameError: global name 'test_directory' is not defined

Patch by Vedant Kumar.

Differential Revision: https://reviews.llvm.org/D51874

llvm-svn: 343726
2018-10-03 21:42:54 +00:00
Louis Dionne 98faa3976d [libc++][NFC] Add error messages to a couple of static_asserts in span
Summary:
Add error messages to a couple of static_asserts in span to match the
style used in the rest of the file. Also fix an extra paren typo in a
assert error message.

Committed on behalf of Jason Lovett.

Reviewers: ldionne

Subscribers: libcxx-commits

Differential Revision: https://reviews.llvm.org/D52841

llvm-svn: 343725
2018-10-03 21:36:16 +00:00
Heejin Ahn 9d224346b2 Make meanings of variables clearer in action table generation (NFC)
Summary:

Reviewers: kristina, zhmu, dschuff, rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52680

llvm-svn: 343724
2018-10-03 21:30:15 +00:00
Craig Topper a65c2dbfd6 [X86] Stop promoting vector ISD::SELECT to vXi64.
The additional patterns needed for this aren't overwhelming and introducing extra bitcasts during lowering limits our ability to do computeNumSignBits. Not that I have a good example of that for select. I'm just becoming increasingly grumpy about promotion of AND/OR/XOR. SELECT was just a lot easier to fix.

llvm-svn: 343723
2018-10-03 21:10:29 +00:00
Fangrui Song f8c4f4e6e7 [ASTMatchers] Fix DynamicASTMatchersTests again
llvm-svn: 343722
2018-10-03 21:00:44 +00:00
Fangrui Song e154d4cbf5 [test] Fix -Wunused-variable in rC343665
llvm-svn: 343721
2018-10-03 20:53:53 +00:00
Stephen Kelly c5ae32a226 Remove stray character from docs
llvm-svn: 343720
2018-10-03 20:53:02 +00:00
Stephen Kelly 719b9f3c58 Update documentation for correctness
llvm-svn: 343719
2018-10-03 20:52:57 +00:00
Shafik Yaghmour d2fcbbab3a Adding skipIf to std::variant libc++ data-formatter test since get is not available before macOS 10.14
Patch by Shafik Yaghmour

llvm-svn: 343718
2018-10-03 20:52:56 +00:00
Stephen Kelly 5834d52d1c Add matchers missing from dynamic AST registry
llvm-svn: 343717
2018-10-03 20:52:51 +00:00
Stephen Kelly 5da85abfa1 Sort list of matchers
llvm-svn: 343716
2018-10-03 20:52:45 +00:00
George Karpenkov 61e48e12b5 [analyzer] [tests] [quickfix] Make the test more resilient for a non-defaut std configuration
llvm-svn: 343715
2018-10-03 20:46:50 +00:00
Sanjay Patel 6916206d32 [InstCombine] add tests for binop undef-into-constant propagation; NFC
llvm-svn: 343714
2018-10-03 20:35:25 +00:00
Craig Topper c39dc41b63 [X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1 SELECT into v8i1.
llvm-svn: 343713
2018-10-03 20:28:43 +00:00
Alex Bradbury ce9049952f [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection
Although we can't write a tablegen pattern to remove redundant 
splitf64+buildf64 pairs due to the multiple return values, we can handle it 
with some C++ selection code. This is simpler than removing them after 
instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was 
done previously.

llvm-svn: 343712
2018-10-03 20:12:10 +00:00
Patrick Lyster 6bdf63bd32 [OPENMP] Add reverse_offload clause to requires directive
llvm-svn: 343711
2018-10-03 20:07:58 +00:00
Craig Topper 703fbde3cb [X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when AVX512VL is enabled.
This allows the phi nodes to be generated with the correct register class when expanded.

llvm-svn: 343710
2018-10-03 19:48:26 +00:00
Craig Topper 4b62c2dbda [X86] Don't break CMOV pseudo instructions down by type. Just by register class.
The register class is all that's important for the pseudo instructions. We can use patterns to handle the different types.

llvm-svn: 343709
2018-10-03 19:48:23 +00:00
Simon Pilgrim aabd99c27a [X86] PUSH/POP 'mem-mem' instructions are not RMW - these are 2 different addresses
This patch adds a 'WriteCopy' [WriteLoad, WriteStore] schedule sequence instead to better model the behaviour

Found by @andreadb during llvm-mca testing on btver2 which was crashing on "zero uop" WriteRMW only instructions

llvm-svn: 343708
2018-10-03 19:02:38 +00:00
Matthew Voss 2016536304 Add template type and value parameter metadata nodes to template variable specializations
Summary: Add an optional attribute referring to a tuple of type and value template parameter nodes to the DIGlobalVariable node. This allows us to record the parameters of template variable specializations.

Reviewers: dblaikie, aprantl, probinson, JDevlieghere, clayborg, jingham

Reviewed By: JDevlieghere

Subscribers: cfe-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D52058

llvm-svn: 343707
2018-10-03 18:45:04 +00:00
Matthew Voss f8ab35a4f4 Emit template type and value parameter DIEs for template variables.
Summary:
Ensure the TemplateParam attribute of the DIGlobalVariable node is translated into the proper DIEs.

Resolves https://bugs.llvm.org/show_bug.cgi?id=22119

Reviewers: dblaikie, probinson, aprantl, JDevlieghere, clayborg, whitequark, deadalnix

Reviewed By: dblaikie

Subscribers: llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D52057

llvm-svn: 343706
2018-10-03 18:44:53 +00:00
Simon Pilgrim b80d27a916 [X86] Move Atomic binops to use WriteALURMW schedule class
These were being tagged as <WriteALULd, WriteRMW> instead of properly using the RMW sequence

llvm-svn: 343705
2018-10-03 18:38:28 +00:00
Martin Storsjo 2657200274 [COFF] Cope with weak aliases produced by GNU tools
When GNU tools create a weak alias, they produce a strong symbol
named .weak.<weaksymbol>.<relatedstrongsymbol>.

GNU ld allows many such weak alternatives for the same weak symbol, and
the linker picks the first one encountered.

This can't be reproduced by assembling from .s files, since llvm-mc
produces symbols named .weak.<weaksymbol>.default in these cases.

Differential Revision: https://reviews.llvm.org/D52601

llvm-svn: 343704
2018-10-03 18:31:53 +00:00
Julie Hockett 73a4d54f81 [clang-doc] Avoid parsing undefined base classes
Don't try to parse base classes for declarations that are not
definitions (segfaults, as there is no DefinitionData to access).

Differential Revision: https://reviews.llvm.org/D52313

llvm-svn: 343703
2018-10-03 18:25:27 +00:00
Martin Storsjo ed9688db30 [test] Use --sysroot instead of -B in print-multi-directory.c
This avoids finding a similar matching GCC installation outside
of the test directory tree in the surrounding environment, which
would make the test fail. (This happened on Ubuntu 16.04.)

Differential Revision: https://reviews.llvm.org/D52533

llvm-svn: 343702
2018-10-03 18:24:05 +00:00
Simon Pilgrim 0b451a2983 [X86][Btver2] Fix MMX PSHUFB schedule
Match AMD Fam16h SOG + llvm-exegesis tests

llvm-svn: 343701
2018-10-03 18:18:50 +00:00
Simon Pilgrim a400612aed [X86] Move Atomic CMPXCHG to WriteCMPXCHGRMW schedule class
llvm-svn: 343700
2018-10-03 18:05:01 +00:00
Mandeep Singh Grang aef87980a9 [COFF, ARM64] Add _ReadWriteBarrier intrinsic
Reviewers: rnk, mstorsjo, compnerd, TomTan, haripul, javed.absar

Reviewed By: rnk

Subscribers: kristof.beyls, chrib, jfb, cfe-commits

Differential Revision: https://reviews.llvm.org/D52809

llvm-svn: 343699
2018-10-03 17:24:21 +00:00
Nico Weber d377826277 lld-link: Several tweaks to default entry point selection.
Three related changes:

1. link.exe uses the presence of main and wmain to decide if it should call
   mainCRTStartup or wmainCRTStartup, even if /nodefaultlib is passed. For
   compatibility, remove FindMain logic.

2. Default to the non-wide entrypoint if main is not found. This has two effects:

2a. In normal links, lld-link now prints

        lld-link: error: undefined symbol: _main
        >>> referenced by f:\dd\vctools\crt\vcstartup\src\startup\exe_common.inl:78
        >>>               libcmt.lib(exe_main.obj):("int __cdecl invoke_main(void)" (?invoke_main@@YAHXZ))
        >>> referenced by f:\dd\vctools\crt\vcstartup\src\startup\exe_common.inl:283
        >>>               libcmt.lib(exe_main.obj):("int __cdecl __scrt_common_main_seh(void)" (?__scrt_common_main_seh@@YAHXZ))

    instead of

        lld-link: error: entry point must be defined

    This is arguably a better error message, since it now mentions that _main is
    missing. (This matches link.exe's diagnostic in this case.)

2b. With /nodefautlib, we now default to mainCRTStartup if no main() is
    present, again matching link.exe. This makes r337407 obsolete.

This means if you have a cc file containing both mainCRTStartup and
wmainCRTStartup and you pass /nodefaultlib /subsystem:console, lld-link will
now call mainCRTStartup, matching link.exe

3. Print a warning if both main and wmain are present, similar to link.exe's
   LNK4067.

Differential Revision: https://reviews.llvm.org/D52832

llvm-svn: 343698
2018-10-03 17:01:39 +00:00
Simon Pilgrim 2c59475c06 [X86] Add SkylakeClient uops counter - same as the other Intel models.
llvm-svn: 343697
2018-10-03 16:45:26 +00:00
Daniel Sanders 10dedc00d0 Correct implementation of -verify-machineinstrs such that it's still overridable for EXPENSIVE_CHECKS
-verify-machineinstrs was implemented as a simple bool. As a result, the
'VerifyMachineCode == cl::BOU_UNSET' used by EXPENSIVE_CHECKS to make it on by
default but possible to disable didn't work as intended. Changed
-verify-machineinstrs to a boolOrDefault to correct this.

llvm-svn: 343696
2018-10-03 16:29:24 +00:00
Adrian Prantl 1c8ed2081f Skip test with older versions of clang
llvm-svn: 343695
2018-10-03 16:24:14 +00:00
Sanjay Patel 306f14ceb8 [InstCombine] clean up foldVectorBinop(); NFC
1. Fix include ordering.
2. Improve variable name (width is bitwidth not number-of-elements).
3. Add local Opcode variable to reduce code duplication.

llvm-svn: 343694
2018-10-03 15:46:03 +00:00
Daniel Sanders fb9b99b26e [globalisel][combines] Don't sink G_TRUNC down to use if that use is a G_PHI
This fixes a problem where the register allocator fails to eliminate a PHI
because there's a non-PHI in the middle of the PHI instructions at the start
of a BB.

This G_TRUNC can be better placed but this at least fixes the correctness issue
quickly. I'll follow up with a patch to the verifier to catch this kind of bug
in future.

llvm-svn: 343693
2018-10-03 15:43:39 +00:00
Sanjay Patel 79dceb2903 [InstCombine] name change: foldShuffledBinop -> foldVectorBinop; NFC
This function will deal with more than shuffles with D50992, and I 
have another potential per-element fold that could live here.

llvm-svn: 343692
2018-10-03 15:20:58 +00:00
Andrea Di Biagio 207e0217f9 [llvm-mca] Add support for move elimination in class RegisterFile.
This patch teaches class RegisterFile how to analyze register writes from
instructions that are move elimination candidates.
In particular, it teaches it how to check if a move can be effectively eliminated
by the underlying PRF, and (if necessary) how to perform move elimination.

The long term goal is to allow processor models to describe instructions that
are valid move elimination candidates.
The idea is to let register file definitions in tablegen declare if/when moves
can be eliminated.

This patch is a non functional change.
The logic that performs move elimination is currently disabled.  A future patch
will add support for move elimination in the processor models, and enable this
new code path.

llvm-svn: 343691
2018-10-03 15:02:44 +00:00
Simon Pilgrim 92d02027c2 [llvm-exegesis] Avoid yaml parser from calling sscanf for obvious non-matches (PR39102)
deserializeMCOperand - ensure that we at least match the first character of the sscanf pattern before calling

This reduces llvm-exegesis uops analysis of the instructions supported from btver2 from 5m13s to 2m1s on debug builds.

llvm-svn: 343690
2018-10-03 14:51:09 +00:00
Nirav Dave 925b64be64 [X86] Correctly use SSE registers if no-x87 is selected.
Fix use of SSE1 registers for f32 ops in no-x87 mode.

Notably, allow use of SSE instructions for f32 operations in 64-bit
mode (but not 32-bit which is disallowed by callign convention).

Also avoid translating memset/memcopy/memmove into SSE registers
without X87 for 32-bit mode.

This fixes PR38738.

Reviewers: nickdesaulniers, craig.topper

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D52555

llvm-svn: 343689
2018-10-03 14:13:30 +00:00
Alex Bradbury d33ffe9bb1 [RISCV][NFC] Refactor RISCVDAGToDAGISel::Select
Introduce and use a switch on the opcode.

llvm-svn: 343688
2018-10-03 13:13:13 +00:00
James Henderson 99031b79a6 [ThinLTO]Expose cache entry expiration time option in llvm-lto and fix a test
Two cases in a ThinLTO test were passing for the wrong reasons, since
rL340374. The tests were supposed to be testing that files were being
pruned due to the cache size, but they were in fact being pruned because
they were older than the default expiration period of 1 week.

This change fixes the tests by explicitly setting the expiration time to
the maximum value. This required the option to be exposed in llvm-lto.

By assigning all files in the cache a similar time, it is possible to see
that the newest files are still being kept, and that we aren't passing
for the wrong reason again. In the event that the entry expiration were
to expire for them, then the test would start failing, because these
files would be removed too.

Reviewed by: rnk, inglorion

Differential Revision: https://reviews.llvm.org/D51992

llvm-svn: 343687
2018-10-03 13:00:20 +00:00
Jonas Paulsson fb3a97bec0 [RA CopyHints] Fix compile-time regression
This patch makes sure that a register is only hinted once to RA. In extreme
cases the same register can otherwise be hinted numerous times and cause a
compile time slowdown.

Review: Simon Pilgrim
https://reviews.llvm.org/D52826

llvm-svn: 343686
2018-10-03 12:51:19 +00:00
Clement Courbet 5a768ddd44 [llvm-exegesis][NFC] Revert rL343682 "Fix unused variable warning".
That was not the proper fix: the variable is used in debug mode.

llvm-svn: 343685
2018-10-03 12:48:50 +00:00
Clement Courbet 8a5a6be47a [llvm-exegesis] Fix rL343680 in release mode.
llvm-svn: 343684
2018-10-03 12:35:35 +00:00
Pavel Labath aef7908f6e Pull FixupBreakpointPCAsNeeded into base class
Summary:
This function existed (with identical code) in both NativeProcessLinux
and NativeProcessNetBSD, and it is likely that it would be useful to any
future implementation of NativeProcessProtocol.

Therefore I move it to the base class.

Reviewers: krytarowski

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D52719

llvm-svn: 343683
2018-10-03 12:29:33 +00:00
Clement Courbet af50a5b85f [llvm-exegesis][NFC] Fix unused variable warning.
llvm-svn: 343682
2018-10-03 12:27:43 +00:00
Aaron Puchert 7146b0032f Thread safety analysis: Unwrap __builtin_expect in getTrylockCallExpr
Summary:
When people are really sure they'll get the lock they sometimes use
__builtin_expect. It's also used by some assertion implementations.
Asserting that try-lock succeeded is basically the same as asserting
that the lock is not held by anyone else (and acquiring it).

Reviewers: aaron.ballman, delesley

Reviewed By: aaron.ballman

Subscribers: kristina, cfe-commits

Differential Revision: https://reviews.llvm.org/D52398

llvm-svn: 343681
2018-10-03 11:58:19 +00:00
Clement Courbet d5a39553ff [llvm-exegesis] Resolve variant classes in analysis.
Summary: See PR38884.

Reviewers: gchatelet

Subscribers: tschuett, RKSimon, llvm-commits

Differential Revision: https://reviews.llvm.org/D52825

llvm-svn: 343680
2018-10-03 11:50:25 +00:00
Alex Bradbury d934032e48 [RISCV] Gate float<->int and double<->int conversion patterns on IsRV32
The patterns as defined are correct only when XLen==32.

This is another preparatory patch for a set of patches that flesh out RV64 
codegen.

llvm-svn: 343679
2018-10-03 11:35:22 +00:00
Alex Bradbury d464ed8c2e [RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates 

This allows the same definitions and patterns to work for RV64 (XLenVT==i64).

llvm-svn: 343678
2018-10-03 11:14:26 +00:00
Alex Bradbury a9ac5994b1 [RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32
These patterns are not correct for RV64.

llvm-svn: 343677
2018-10-03 11:04:59 +00:00