09487775d3
ARM: Add test cleanup entry to the README.
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llvm-svn: 159864
2012-07-06 21:52:04 +00:00
0a5b72f0e4
Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr.
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A MOVCCr instruction can be commuted by inverting the condition. This
can help reduce register pressure and remove unnecessary copies in some
cases.
<rdar://problem/11182914>
llvm-svn: 154033
2012-04-04 18:23:42 +00:00
de0c335560
Add a note about a potential optimization for clz/ctz patterns for ARM
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(and other targets).
llvm-svn: 149182
2012-01-28 18:30:07 +00:00
21e9051922
Add an entry.
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llvm-svn: 135024
2011-07-13 01:33:00 +00:00
ab8881accd
Add a readme entry for the redundant movw issue for pr9370.
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llvm-svn: 126930
2011-03-03 06:39:09 +00:00
f902befe8e
And a bit more non-ASCII stuff.
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llvm-svn: 109458
2010-07-26 22:28:18 +00:00
1e0d76bfd1
Drop some non-ascii stuff
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llvm-svn: 109456
2010-07-26 22:23:07 +00:00
b61a6f2742
Add a note
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llvm-svn: 109448
2010-07-26 21:48:35 +00:00
b97e2bbe32
Add combiner patterns to more effectively utilize the BFI (bitfield insert)
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instruction for non-constant operands. This includes the case referenced
in the README.txt regarding a bitfield copy.
llvm-svn: 108608
2010-07-17 03:30:54 +00:00
e4be4308a9
Random note about bswap.
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llvm-svn: 108396
2010-07-15 02:20:38 +00:00
c4d70125ee
A couple potential optimizations inspired by comment 4 in PR6773.
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llvm-svn: 108328
2010-07-14 06:58:26 +00:00
9bc1ed9962
add a note.
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llvm-svn: 99815
2010-03-29 17:02:02 +00:00
cb80e2527e
add a note, from PR5100
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llvm-svn: 96490
2010-02-17 18:42:24 +00:00
08297ad15d
this is done, tested by CodeGen/ARM/iabs.ll
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llvm-svn: 95609
2010-02-08 23:48:10 +00:00
267430f74d
Fix PR5694. The CMN instructions set the flags differently from CMP, so they
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cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.
llvm-svn: 94119
2010-01-22 00:08:13 +00:00
d7cf55cd0e
Use Unified Assembly Syntax for the ARM backend.
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llvm-svn: 86494
2009-11-09 00:11:35 +00:00
a8e8a7c976
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
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llvm-svn: 86330
2009-11-07 04:04:34 +00:00
115cfc07d5
These are done / no longer care.
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llvm-svn: 85798
2009-11-02 07:58:25 +00:00
f6f1b37f9f
Add an entry.
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llvm-svn: 85797
2009-11-02 07:51:19 +00:00
c7415bf536
Add a note about Robert Muth's alternate jump table implementation.
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llvm-svn: 85624
2009-10-30 22:22:46 +00:00
83e0d481ae
Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
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instruction. This makes it re-materializable.
Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.
llvm-svn: 82982
2009-09-28 09:14:39 +00:00
c667b60b93
add a random codegen deficiency.
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llvm-svn: 77598
2009-07-30 16:08:58 +00:00
c26c76ec1d
Disable my constant island pass optimization (to make use soimm more effectively). It caused infinite looping on lencod.
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llvm-svn: 76995
2009-07-24 19:31:03 +00:00
c7a243dfdd
Add an entry.
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llvm-svn: 76711
2009-07-22 00:58:27 +00:00
b23b50d54d
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
e2c4d35f3e
Add a note about commuting conditional move.
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llvm-svn: 74241
2009-06-26 00:28:48 +00:00
cf661fc12a
These are done / no longer applicable.
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llvm-svn: 74239
2009-06-26 00:25:27 +00:00
2e076c4e02
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
57662f3882
several entries got significantly better, though they still aren't done.
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llvm-svn: 44382
2007-11-27 22:41:52 +00:00
f3f4ad9dd6
implement a trivial readme entry.
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llvm-svn: 44380
2007-11-27 22:36:16 +00:00
5d979d57ae
Add an easy microoptimization I noticed.
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llvm-svn: 43164
2007-10-19 03:29:26 +00:00
6777b72659
Add some notes about better flag handling.
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llvm-svn: 41808
2007-09-10 21:43:18 +00:00
effa7467b6
Update.
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llvm-svn: 38513
2007-07-10 21:49:47 +00:00
8dd36a51fc
Remove item: thumb padding in constant islands
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llvm-svn: 36586
2007-04-30 00:32:06 +00:00
3d3f22766a
add a crazy idea
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llvm-svn: 36273
2007-04-20 20:18:43 +00:00
2509d7547d
add a note
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llvm-svn: 36203
2007-04-17 18:03:00 +00:00
cba9538499
Updated.
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llvm-svn: 35229
2007-03-20 22:32:39 +00:00
09663aeac7
Minor stuff.
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llvm-svn: 35049
2007-03-09 19:46:06 +00:00
31ef0ab7cf
Add comments about LSR / ARM.
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llvm-svn: 35048
2007-03-09 19:35:33 +00:00
603f3094eb
Unfinished work and ideas related to register scavenger.
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llvm-svn: 35047
2007-03-09 19:34:51 +00:00
368faf9acd
apply comments from review of last patch
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llvm-svn: 35045
2007-03-09 19:18:59 +00:00
af0cff2671
Add some observations from CoreGraphics benchmark. Remove register
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scavenging todo item, since it is now implemented.
llvm-svn: 35044
2007-03-09 17:58:17 +00:00
440995bd9a
Add intelligence about where to break large blocks.
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llvm-svn: 34755
2007-02-28 18:41:23 +00:00
c2f3d015e0
cosmetic changes from review of last patch. obvious
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llvm-svn: 34598
2007-02-25 18:31:31 +00:00
01ee5750f4
Removed WaterListOffset, inserted BBOffsets. Remove TODO item about this
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from README.
When no water available, use end of block if in range. (More to do here.)
llvm-svn: 34563
2007-02-25 00:47:03 +00:00
e18b13b213
rewrite of constant islands
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llvm-svn: 34523
2007-02-23 05:02:36 +00:00
2d5b4ac38f
add a note
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llvm-svn: 33778
2007-02-02 04:36:46 +00:00
10043e215b
ARM backend contribution from Apple.
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llvm-svn: 33353
2007-01-19 07:51:42 +00:00
eb3e8d75df
add note
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llvm-svn: 32452
2006-12-11 23:56:10 +00:00
418c8e69bb
add FSTD and FSTS
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llvm-svn: 30996
2006-10-17 13:36:07 +00:00
Jim Grosbach