Commit Graph

42 Commits

Author SHA1 Message Date
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Jakob Stoklund Olesen bdb55e0c59 Use MCPhysReg for RegisterClassInfo allocation orders.
This saves a bit of memory.

llvm-svn: 168852
2012-11-29 03:34:17 +00:00
Jakob Stoklund Olesen f67bf3e0ea Remove RegisterClassInfo::isReserved() and isAllocatable().
Clients can use the equivalent functions in MRI.

llvm-svn: 165990
2012-10-15 22:41:03 +00:00
Benjamin Kramer bde9176663 Fix typos found by http://github.com/lyda/misspell-check
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
Jakob Stoklund Olesen 54038d796c Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854
2012-06-01 23:28:30 +00:00
Jakob Stoklund Olesen 92a0083944 Switch some getAliasSet clients to MCRegAliasIterator.
MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

llvm-svn: 157837
2012-06-01 20:36:54 +00:00
Jakob Stoklund Olesen 3c52f0281f Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328
2012-05-07 22:10:26 +00:00
Benjamin Kramer 5d1bca8016 CriticalAntiDepBreaker: Replace a SmallSet of regs with a much denser BitVector.
llvm-svn: 152999
2012-03-17 20:22:57 +00:00
Benjamin Kramer 8e5af375db CriticalAntiDepBreaker: BasicBlock::size is an expensive operation, reuse the cached value.
No functionality change.

llvm-svn: 152927
2012-03-16 15:46:47 +00:00
Craig Topper 4b02a29eba Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
llvm-svn: 152016
2012-03-05 05:37:41 +00:00
Craig Topper 1d32658877 Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
Craig Topper 420525ce3b Use uint16_t to store registers in callee saved register tables to reduce size of static data.
llvm-svn: 151996
2012-03-04 03:33:22 +00:00
Jakob Stoklund Olesen 38ce889cb6 Handle regmasks in CriticalAntiDepBreaker.
llvm-svn: 151223
2012-02-23 01:15:26 +00:00
Andrew Trick 46cc9a4aaa Initialize SUnits before DAG building.
Affect on SD scheduling and postRA scheduling:
Printing the DAG will display the nodes in top-down topological order.
This matches the order within the MBB and makes my life much easier in general.

Affect on misched:
We don't need to track virtual register uses at all. This is awesome.
I also intend to rely on the SUnit ID as a topo-sort index. So if A < B then we cannot have an edge B -> A.

llvm-svn: 151135
2012-02-22 06:08:11 +00:00
Evan Cheng 00b1a3cd7e Added a late machine instruction copy propagation pass. This catches
opportunities that only present themselves after late optimizations
such as tail duplication .e.g.
## BB#1:
        movl    %eax, %ecx
        movl    %ecx, %eax
        ret

The register allocator also leaves some of them around (due to false
dep between copies from phi-elimination, etc.)

This required some changes in codegen passes. Post-ra scheduler and the
pseudo-instruction expansion passes have been moved after branch folding
and tail merging. They were before branch folding before because it did
not always update block livein's. That's fixed now. The pass change makes
independently since we want to properly schedule instructions after
branch folding / tail duplication.

rdar://10428165
rdar://10640363

llvm-svn: 147716
2012-01-07 03:02:36 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Evan Cheng 8d71a75777 More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
llvm-svn: 133944
2011-06-27 21:26:13 +00:00
Jakob Stoklund Olesen 4f5f84c7e7 Teach antidependency breakers to use RegisterClassInfo.
No functional change was intended.

llvm-svn: 133202
2011-06-16 21:56:21 +00:00
Devang Patel f02a376fbc Update DBG_VALUEs while breaking anti dependencies.
llvm-svn: 132487
2011-06-02 21:26:52 +00:00
Andrew Trick 4b4918788b Fix PostRA antidependence breaker.
Avoid using the same register for two def operands or and earlyclobber
def and use operand. This fixes PR8986 and improves on the prior fix
for rdar://problem/8959122.

llvm-svn: 125089
2011-02-08 17:39:46 +00:00
Andrew Trick f841571404 Fix an anti-dep breaker corner case.
<rdar://problem/8959122> illegal register operands for UMULL instruction in cfrac nightly test
I'm stil working on a unit test, but the case is:
rx = movcc rx, r3
r2 = ldr
r2, r3 = umull r2, r2

The anti-dep breaker should not convert this into an illegal instruction:
r2, r2 = umull

llvm-svn: 124932
2011-02-05 02:58:46 +00:00
Andrew Trick 82ae9a95a5 Fixes <rdar://problem/8612856>: During postRAsched, the antidependence
breaker needs to check all definitions of the antidepenent register to
avoid multiple defs of the same new register.

llvm-svn: 118032
2010-11-02 18:16:45 +00:00
Bob Wilson c57c220d20 Fix a miscompile in 186.crafty for Thumb2 that was exposed by Evan's
scheduling change in svn 115121.  The CriticalAntiDepBreaker had bad
liveness information.  It was calculating the KillIndices for one scheduling
region in a basic block, rescheduling that region so the KillIndices were
no longer valid, and then using those wrong KillIndices to make decisions
for the next scheduling region.  I've not been able to reduce a small
testcase for this.  Radar 8502534.

llvm-svn: 115400
2010-10-02 01:49:29 +00:00
Bob Wilson f3ecfd0e53 Fix a comment typo.
llvm-svn: 113653
2010-09-10 22:42:21 +00:00
Jim Grosbach 944aece38a Anti-dependency breaking needs to be careful not to use reserved regs
llvm-svn: 112832
2010-09-02 17:12:55 +00:00
Dan Gohman c2af77f510 Fix a use-after-free.
llvm-svn: 109468
2010-07-26 23:40:24 +00:00
Bill Wendling 51a9c0a1b3 Use std::vector instead of TargetRegisterInfo::FirstVirtualRegister. This time
make sure to allocate enough space in the std::vector.

llvm-svn: 108449
2010-07-15 19:58:14 +00:00
Chris Lattner c48adb60ca revert bill's patches in an attempt to fix the buildbot.
llvm-svn: 108419
2010-07-15 06:51:46 +00:00
Bill Wendling d5b390189d Use std::vector instead of a hard-coded array. The length of that array could
get *very* large, but we only need it to be the size of thenumber of pregs.

llvm-svn: 108411
2010-07-15 05:56:32 +00:00
Evan Cheng f128bdcb55 Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
llvm-svn: 106091
2010-06-16 07:35:02 +00:00
Jim Grosbach 848548300d Not all entries in the range will have an SUnit. Check for that when looking
for debug information.

llvm-svn: 105324
2010-06-02 15:29:36 +00:00
Jim Grosbach 12ac8f0352 Update debug information when breaking anti-dependencies. rdar://7759363
llvm-svn: 105300
2010-06-01 23:48:44 +00:00
Jim Grosbach 866b74ba8b Remove trailing whitespace
llvm-svn: 103807
2010-05-14 21:20:46 +00:00
Dan Gohman 35bc4d46cb Make BreakAntiDependencies' SUnits argument const, and make the Begin
and End arguments by-value rather than by-reference.

llvm-svn: 101830
2010-04-19 23:11:58 +00:00
Dale Johannesen 2061c84109 Fix some more places where dbg_value affected codegen.
llvm-svn: 97765
2010-03-05 00:02:59 +00:00
Jim Grosbach a7cef4fab5 Anti-dependency breaking needs to be careful regarding instructions with
multiple register definitions.

llvm-svn: 92864
2010-01-06 22:21:25 +00:00
Jim Grosbach eb431da074 80 column and whitespace cleanup
llvm-svn: 92837
2010-01-06 16:48:02 +00:00
David Greene 96b90539d6 Change errs() to dbgs().
llvm-svn: 92490
2010-01-04 17:47:05 +00:00
David Goodwin a45fe67667 <rdar://problem/7453528>. Track only physical registers that are valid for the target.
llvm-svn: 90970
2009-12-09 17:18:22 +00:00
David Goodwin 80a03cc0b1 Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.
llvm-svn: 89471
2009-11-20 19:32:48 +00:00
David Goodwin 8501dbbe10 Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.
llvm-svn: 85939
2009-11-03 20:57:50 +00:00
David Goodwin 8370485db9 Break anti-dependence breaking out into its own class.
llvm-svn: 85127
2009-10-26 16:59:04 +00:00