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[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic 

mfvrd and mffprd are both alias to mfvrsd.
This patch enables correct parsing of the aliases, but we still emit a mfvrsd.

Committing on behalf of brunoalr (Bruno Rosa).

Differential Revision: https://reviews.llvm.org/D29177

llvm-svn: 297849
This commit is contained in:
Nemanja Ivanovic 2017-03-15 16:04:53 +00:00
parent 503206c567
commit ffcf0fb1cc
7 changed files with 195 additions and 453 deletions
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12
llvm/lib/Target/PowerPC/PPCInstrVSX.td
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@ -1410,6 +1410,11 @@ let Predicates = [HasDirectMove] in {
"mfvsrd $rA, $XT", IIC_VecGeneral,
[(set i64:$rA, (PPCmfvsr f64:$XT))]>,
Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in
def MFVRD : XX1_RS6_RD5_XO<31, 51, (outs g8rc:$rA), (ins vrrc:$XT),
"mfvsrd $rA, $XT", IIC_VecGeneral,
[]>,
Requires<[In64BitMode]>;
def MFVSRWZ : XX1_RS6_RD5_XO<31, 115, (outs gprc:$rA), (ins vsfrc:$XT),
"mfvsrwz $rA, $XT", IIC_VecGeneral,
[(set i32:$rA, (PPCmfvsr f64:$XT))]>;
@ -1440,6 +1445,13 @@ let Predicates = [IsISA3_0, HasDirectMove] in {
} // IsISA3_0, HasDirectMove
} // UseVSXReg = 1
// We want to parse this from asm, but we don't want to emit this as it would
// be emitted with a VSX reg. So leave Emit = 0 here.
def : InstAlias<"mfvrd $rA, $XT",
(MFVRD g8rc:$rA, vrrc:$XT), 0>;
def : InstAlias<"mffprd $rA, $src",
(MFVSRD g8rc:$rA, f8rc:$src)>;
/* Direct moves of various widths from GPR's into VSR's. Each move lines
the value up into element 0 (both BE and LE). Namely, entities smaller than
a doubleword are shifted left and moved for BE. For LE, they're moved, then

4
llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
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@ -20,7 +20,7 @@ entry:
ret i64 %0
; CHECK-P7: stxsdx 1,
; CHECK-P7: ld 3,
; CHECK: mfvsrd 3, 1
; CHECK: mffprd 3, 1
}
define float @i32tof32(i32 signext %a) {
@ -60,7 +60,7 @@ entry:
ret i64 %0
; CHECK-P7: stxsdx 1,
; CHECK-P7: ld 3,
; CHECK: mfvsrd 3, 1
; CHECK: mffprd 3, 1
}
define float @i32utof32(i32 zeroext %a) {

8
llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll
View File

@ -323,7 +323,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z7testllff
; CHECK: xscvdpsxds [[CONVREG13:[0-9]+]], 1
; CHECK: mfvsrd 3, [[CONVREG13]]
; CHECK: mffprd 3, [[CONVREG13]]
}
; Function Attrs: nounwind
@ -349,7 +349,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z7testlldd
; CHECK: xscvdpsxds [[CONVREG14:[0-9]+]], 1
; CHECK: mfvsrd 3, [[CONVREG14]]
; CHECK: mffprd 3, [[CONVREG14]]
}
; Function Attrs: nounwind
@ -375,7 +375,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z8testullff
; CHECK: xscvdpuxds [[CONVREG15:[0-9]+]], 1
; CHECK: mfvsrd 3, [[CONVREG15]]
; CHECK: mffprd 3, [[CONVREG15]]
}
; Function Attrs: nounwind
@ -401,7 +401,7 @@ entry:
ret i64 %conv
; CHECK-LABEL: @_Z8testulldd
; CHECK: xscvdpuxds [[CONVREG16:[0-9]+]], 1
; CHECK: mfvsrd 3, [[CONVREG16]]
; CHECK: mffprd 3, [[CONVREG16]]
}
; Function Attrs: nounwind

10
llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
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@ -19,8 +19,8 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_abs:
; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: rldicr [[FLIP_BIT:[0-9]+]], [[HI]], 0, 0
; PPC64-P8-DAG: xor 3, [[HI]], [[FLIP_BIT]]
; PPC64-P8-DAG: xor 4, [[LO]], [[FLIP_BIT]]
@ -59,8 +59,8 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_neg:
; PPC64-P8-DAG: mfvsrd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mfvsrd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: mffprd [[LO:[0-9]+]], 2
; PPC64-P8-DAG: mffprd [[HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[IMM1:[0-9]+]], 1
; PPC64-P8-DAG: sldi [[FLIP_BIT:[0-9]+]], [[IMM1]], 63
; PPC64-P8-NOT: BARRIER
@ -101,7 +101,7 @@ entry:
; PPC64: blr
; PPC64-P8-LABEL: test_copysign:
; PPC64-P8-DAG: mfvsrd [[X_HI:[0-9]+]], 1
; PPC64-P8-DAG: mffprd [[X_HI:[0-9]+]], 1
; PPC64-P8-DAG: li [[HI_TMP:[0-9]+]], 16399
; PPC64-P8-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48
; PPC64-P8-DAG: li [[LO_TMP:[0-9]+]], 3019

601
llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
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File diff suppressed because it is too large Load Diff

4
llvm/test/MC/Disassembler/PowerPC/vsx.txt
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@ -525,8 +525,8 @@
# CHECK: xxswapd 7, 63
0xf0 0xff 0xfa 0x56
# CHECK: mfvsrd 3, 0
0x7c 0x03 0x00 0x66
# CHECK: mfvsrd 3, 40
0x7d 0x03 0x00 0x67
# CHECK: mfvsrwz 5, 0
0x7c 0x05 0x00 0xe6

9
llvm/test/MC/PowerPC/vsx.s
View File

@ -532,9 +532,12 @@
xxswapd 7, 63
# Move to/from VSR
# CHECK-BE: mfvsrd 3, 0 # encoding: [0x7c,0x03,0x00,0x66]
# CHECK-LE: mfvsrd 3, 0 # encoding: [0x66,0x00,0x03,0x7c]
mfvsrd 3, 0
# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
mfvsrd 3, 40
# CHECK-BE: mfvsrd 3, 40 # encoding: [0x7d,0x03,0x00,0x67]
# CHECK-LE: mfvsrd 3, 40 # encoding: [0x67,0x00,0x03,0x7d]
mfvrd 3, 8
# CHECK-BE: mfvsrwz 5, 0 # encoding: [0x7c,0x05,0x00,0xe6]
# CHECK-LE: mfvsrwz 5, 0 # encoding: [0xe6,0x00,0x05,0x7c]
mfvsrwz 5, 0