parent
4242d48c36
commit
ff7e5aadf5
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@ -2813,6 +2813,8 @@ static bool fnegFoldsIntoOp(unsigned Opc) {
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case ISD::FMUL:
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case ISD::FMA:
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case ISD::FMAD:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RCP_LEGACY:
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return true;
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default:
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return false;
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@ -2899,10 +2901,13 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
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DAG.ReplaceAllUsesWith(N0, DAG.getNode(ISD::FNEG, SL, VT, Res));
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return Res;
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}
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case ISD::FP_EXTEND: {
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case ISD::FP_EXTEND:
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case AMDGPUISD::RCP:
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case AMDGPUISD::RCP_LEGACY: {
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SDValue CvtSrc = N0.getOperand(0);
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if (CvtSrc.getOpcode() == ISD::FNEG) {
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// (fneg (fp_extend (fneg x))) -> (fp_extend x)
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// (fneg (rcp (fneg x))) -> (rcp x)
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return DAG.getNode(Opc, SL, VT, CvtSrc.getOperand(0));
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}
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@ -2910,6 +2915,7 @@ SDValue AMDGPUTargetLowering::performFNegCombine(SDNode *N,
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return SDValue();
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// (fneg (fp_extend x)) -> (fp_extend (fneg x))
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// (fneg (rcp x)) -> (rcp (fneg x))
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SDValue Neg = DAG.getNode(ISD::FNEG, SL, CvtSrc.getValueType(), CvtSrc);
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return DAG.getNode(Opc, SL, VT, Neg);
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}
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@ -954,9 +954,109 @@ define void @v_fneg_fp_round_multi_use_fneg_f32_to_f16(half addrspace(1)* %out,
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ret void
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}
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; --------------------------------------------------------------------------------
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; rcp tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_rcp_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rcp_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_rcp_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%rcp = call float @llvm.amdgcn.rcp.f32(float %a)
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%fneg = fsub float -0.000000e+00, %rcp
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_rcp_fneg_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_rcp_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
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%fneg = fsub float -0.000000e+00, %rcp
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_rcp_store_use_fneg_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN-DAG: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
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; GCN-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
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; GCN: buffer_store_dword [[RESULT]]
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; GCN: buffer_store_dword [[NEG_A]]
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define void @v_fneg_rcp_store_use_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
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%fneg = fsub float -0.000000e+00, %rcp
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store volatile float %fneg, float addrspace(1)* %out.gep
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store volatile float %fneg.a, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_fneg_rcp_multi_use_fneg_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN-DAG: v_rcp_f32_e32 [[RESULT:v[0-9]+]], [[A]]
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; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
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; GCN: buffer_store_dword [[RESULT]]
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; GCN: buffer_store_dword [[MUL]]
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define void @v_fneg_rcp_multi_use_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float %c) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%fneg.a = fsub float -0.000000e+00, %a
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%rcp = call float @llvm.amdgcn.rcp.f32(float %fneg.a)
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%fneg = fsub float -0.000000e+00, %rcp
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%use1 = fmul float %fneg.a, %c
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store volatile float %fneg, float addrspace(1)* %out.gep
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store volatile float %use1, float addrspace(1)* undef
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ret void
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}
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; --------------------------------------------------------------------------------
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; rcp_legacy tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_rcp_legacy_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rcp_legacy_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: buffer_store_dword [[RESULT]]
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define void @v_fneg_rcp_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%rcp = call float @llvm.amdgcn.rcp.legacy(float %a)
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%fneg = fsub float -0.000000e+00, %rcp
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fma.f32(float, float, float) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare float @llvm.amdgcn.rcp.f32(float) #1
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declare float @llvm.amdgcn.rcp.legacy(float) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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