diff --git a/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll b/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll index 9c71469b5b20..4feb764bec6b 100644 --- a/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll +++ b/llvm/test/CodeGen/X86/2009-01-13-DoubleUpdate.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx -enable-legalize-types-checking +; RUN: llc < %s -march=x86 -mattr=+sse2 -enable-legalize-types-checking declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone diff --git a/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll b/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll index eb9378b9527b..366985678e54 100644 --- a/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll +++ b/llvm/test/CodeGen/X86/2009-07-07-SplitICmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -disable-mmx +; RUN: llc < %s -march=x86 define void @test2(<2 x i32> %A, <2 x i32> %B, <2 x i32>* %C) nounwind { %D = icmp sgt <2 x i32> %A, %B diff --git a/llvm/test/CodeGen/X86/bc-extract.ll b/llvm/test/CodeGen/X86/bc-extract.ll index 6e8063ad7c0e..ac972a8e2e5b 100644 --- a/llvm/test/CodeGen/X86/bc-extract.ll +++ b/llvm/test/CodeGen/X86/bc-extract.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s define float @extractFloat1() nounwind { diff --git a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll index 5cc6eaa405ad..dae91d5ccdd6 100644 --- a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll +++ b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s ; Shows a dag combine bug that will generate an illegal build vector ; with v2i64 build_vector i32, i32. diff --git a/llvm/test/CodeGen/X86/insertelement-legalize.ll b/llvm/test/CodeGen/X86/insertelement-legalize.ll index 18aade2bb302..3805cbbaaaf8 100644 --- a/llvm/test/CodeGen/X86/insertelement-legalize.ll +++ b/llvm/test/CodeGen/X86/insertelement-legalize.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -disable-mmx +; RUN: llc < %s -march=x86 ; Test to check that we properly legalize an insert vector element define void @test(<2 x i64> %val, <2 x i64>* %dst, i64 %x) nounwind { diff --git a/llvm/test/CodeGen/X86/legalizedag_vec.ll b/llvm/test/CodeGen/X86/legalizedag_vec.ll index 028627d3c093..dff693120fb6 100644 --- a/llvm/test/CodeGen/X86/legalizedag_vec.ll +++ b/llvm/test/CodeGen/X86/legalizedag_vec.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=sse2 | FileCheck %s ; Test case for r63760 where we generate a legalization assert that an illegal diff --git a/llvm/test/CodeGen/X86/scalar_widen_div.ll b/llvm/test/CodeGen/X86/scalar_widen_div.ll index 77f320f1056e..adc58ac34b9e 100644 --- a/llvm/test/CodeGen/X86/scalar_widen_div.ll +++ b/llvm/test/CodeGen/X86/scalar_widen_div.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -disable-mmx -march=x86-64 -mattr=+sse42 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s ; Verify when widening a divide/remainder operation, we only generate a ; divide/rem per element since divide/remainder can trap. diff --git a/llvm/test/CodeGen/X86/vec-trunc-store.ll b/llvm/test/CodeGen/X86/vec-trunc-store.ll index 2f57d7b571f0..4d665f1843ef 100644 --- a/llvm/test/CodeGen/X86/vec-trunc-store.ll +++ b/llvm/test/CodeGen/X86/vec-trunc-store.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -disable-mmx >/dev/null +; RUN: llc < %s -march=x86-64 define void @foo(<8 x i32>* %p) nounwind { %t = load <8 x i32>* %p diff --git a/llvm/test/CodeGen/X86/vec_cast.ll b/llvm/test/CodeGen/X86/vec_cast.ll index f8531646effa..95289c9685a1 100644 --- a/llvm/test/CodeGen/X86/vec_cast.ll +++ b/llvm/test/CodeGen/X86/vec_cast.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 -mcpu=core2 -; RUN: llc < %s -march=x86-64 -mcpu=core2 -disable-mmx define <8 x i32> @a(<8 x i16> %a) nounwind { diff --git a/llvm/test/CodeGen/X86/vec_compare-2.ll b/llvm/test/CodeGen/X86/vec_compare-2.ll index 091641b3bc3b..04bb7254fb08 100644 --- a/llvm/test/CodeGen/X86/vec_compare-2.ll +++ b/llvm/test/CodeGen/X86/vec_compare-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=penryn -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=penryn | FileCheck %s declare <4 x float> @llvm.x86.sse41.blendvps(<4 x float>, <4 x float>, <4 x float>) nounwind readnone diff --git a/llvm/test/CodeGen/X86/vec_ext_inreg.ll b/llvm/test/CodeGen/X86/vec_ext_inreg.ll index 8d2a3c31aedf..02b16a79f4a0 100644 --- a/llvm/test/CodeGen/X86/vec_ext_inreg.ll +++ b/llvm/test/CodeGen/X86/vec_ext_inreg.ll @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 -; RUN: llc < %s -march=x86-64 -disable-mmx define <8 x i32> @a(<8 x i32> %a) nounwind { %b = trunc <8 x i32> %a to <8 x i16> diff --git a/llvm/test/CodeGen/X86/vec_shuffle-30.ll b/llvm/test/CodeGen/X86/vec_shuffle-30.ll index 3f69150ac533..1651c4cdace2 100644 --- a/llvm/test/CodeGen/X86/vec_shuffle-30.ll +++ b/llvm/test/CodeGen/X86/vec_shuffle-30.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=sse41 -disable-mmx -o %t +; RUN: llc < %s -march=x86 -mattr=sse41 -o %t ; RUN: grep pshufhw %t | grep -- -95 | count 1 ; RUN: grep shufps %t | count 1 ; RUN: not grep pslldq %t diff --git a/llvm/test/CodeGen/X86/vshift-1.ll b/llvm/test/CodeGen/X86/vshift-1.ll index ae845e0a33d1..49551562c5ae 100644 --- a/llvm/test/CodeGen/X86/vshift-1.ll +++ b/llvm/test/CodeGen/X86/vshift-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; test vector shifts converted to proper SSE2 vector shifts when the shift ; amounts are the same. diff --git a/llvm/test/CodeGen/X86/vshift-2.ll b/llvm/test/CodeGen/X86/vshift-2.ll index 36feb11603d8..9a9b419abea5 100644 --- a/llvm/test/CodeGen/X86/vshift-2.ll +++ b/llvm/test/CodeGen/X86/vshift-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; test vector shifts converted to proper SSE2 vector shifts when the shift ; amounts are the same. diff --git a/llvm/test/CodeGen/X86/vshift-3.ll b/llvm/test/CodeGen/X86/vshift-3.ll index 20d3f48a1a67..8e8a9aa04b27 100644 --- a/llvm/test/CodeGen/X86/vshift-3.ll +++ b/llvm/test/CodeGen/X86/vshift-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; test vector shifts converted to proper SSE2 vector shifts when the shift ; amounts are the same. diff --git a/llvm/test/CodeGen/X86/vshift-4.ll b/llvm/test/CodeGen/X86/vshift-4.ll index 9773cbed0ae3..8e24fda1835d 100644 --- a/llvm/test/CodeGen/X86/vshift-4.ll +++ b/llvm/test/CodeGen/X86/vshift-4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; test vector shifts converted to proper SSE2 vector shifts when the shift ; amounts are the same when using a shuffle splat. diff --git a/llvm/test/CodeGen/X86/vshift-5.ll b/llvm/test/CodeGen/X86/vshift-5.ll index a543f382b513..cb254aeb5735 100644 --- a/llvm/test/CodeGen/X86/vshift-5.ll +++ b/llvm/test/CodeGen/X86/vshift-5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s ; When loading the shift amount from memory, avoid generating the splat. diff --git a/llvm/test/CodeGen/X86/vsplit-and.ll b/llvm/test/CodeGen/X86/vsplit-and.ll index a247c6eb00d7..97dacfdf09e0 100644 --- a/llvm/test/CodeGen/X86/vsplit-and.ll +++ b/llvm/test/CodeGen/X86/vsplit-and.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 | FileCheck %s define void @t(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly { diff --git a/llvm/test/CodeGen/X86/widen_arith-1.ll b/llvm/test/CodeGen/X86/widen_arith-1.ll index f8d06902c553..4b8016dc7132 100644 --- a/llvm/test/CodeGen/X86/widen_arith-1.ll +++ b/llvm/test/CodeGen/X86/widen_arith-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; Widen a v3i8 to v16i8 to use a vector add diff --git a/llvm/test/CodeGen/X86/widen_arith-2.ll b/llvm/test/CodeGen/X86/widen_arith-2.ll index fdecaa3f77ff..03b3fea01f6c 100644 --- a/llvm/test/CodeGen/X86/widen_arith-2.ll +++ b/llvm/test/CodeGen/X86/widen_arith-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: paddb ; CHECK: pand diff --git a/llvm/test/CodeGen/X86/widen_arith-3.ll b/llvm/test/CodeGen/X86/widen_arith-3.ll index 1f2c25068ca4..057492377a27 100644 --- a/llvm/test/CodeGen/X86/widen_arith-3.ll +++ b/llvm/test/CodeGen/X86/widen_arith-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s ; CHECK: paddw ; CHECK: pextrw ; CHECK: movd diff --git a/llvm/test/CodeGen/X86/widen_arith-4.ll b/llvm/test/CodeGen/X86/widen_arith-4.ll index f7506ae3e3cd..5931d639f19b 100644 --- a/llvm/test/CodeGen/X86/widen_arith-4.ll +++ b/llvm/test/CodeGen/X86/widen_arith-4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s ; CHECK: psubw ; CHECK-NEXT: pmullw diff --git a/llvm/test/CodeGen/X86/widen_arith-5.ll b/llvm/test/CodeGen/X86/widen_arith-5.ll index bae5c54eea64..7f2eff09f473 100644 --- a/llvm/test/CodeGen/X86/widen_arith-5.ll +++ b/llvm/test/CodeGen/X86/widen_arith-5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s ; CHECK: movdqa ; CHECK: pmulld ; CHECK: psubd diff --git a/llvm/test/CodeGen/X86/widen_arith-6.ll b/llvm/test/CodeGen/X86/widen_arith-6.ll index 538123f10c25..b983d141ddf6 100644 --- a/llvm/test/CodeGen/X86/widen_arith-6.ll +++ b/llvm/test/CodeGen/X86/widen_arith-6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: mulps ; CHECK: addps diff --git a/llvm/test/CodeGen/X86/widen_cast-1.ll b/llvm/test/CodeGen/X86/widen_cast-1.ll index d4ab174ae9fb..1eace9e024e0 100644 --- a/llvm/test/CodeGen/X86/widen_cast-1.ll +++ b/llvm/test/CodeGen/X86/widen_cast-1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 -mattr=+sse42 < %s -disable-mmx | FileCheck %s +; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s ; CHECK: paddw ; CHECK: pextrd ; CHECK: movd diff --git a/llvm/test/CodeGen/X86/widen_cast-2.ll b/llvm/test/CodeGen/X86/widen_cast-2.ll index 14e8f7562482..5c695ea00033 100644 --- a/llvm/test/CodeGen/X86/widen_cast-2.ll +++ b/llvm/test/CodeGen/X86/widen_cast-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: pextrd ; CHECK: pextrd ; CHECK: movd diff --git a/llvm/test/CodeGen/X86/widen_cast-3.ll b/llvm/test/CodeGen/X86/widen_cast-3.ll index 02674dd1459c..87486d96611b 100644 --- a/llvm/test/CodeGen/X86/widen_cast-3.ll +++ b/llvm/test/CodeGen/X86/widen_cast-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: paddd ; CHECK: pextrd ; CHECK: pextrd diff --git a/llvm/test/CodeGen/X86/widen_cast-4.ll b/llvm/test/CodeGen/X86/widen_cast-4.ll index 5f31e560f500..8e1adf58f869 100644 --- a/llvm/test/CodeGen/X86/widen_cast-4.ll +++ b/llvm/test/CodeGen/X86/widen_cast-4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: sarb ; CHECK: sarb ; CHECK: sarb diff --git a/llvm/test/CodeGen/X86/widen_cast-5.ll b/llvm/test/CodeGen/X86/widen_cast-5.ll index d1d7fecbd275..136578df1e8e 100644 --- a/llvm/test/CodeGen/X86/widen_cast-5.ll +++ b/llvm/test/CodeGen/X86/widen_cast-5.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: movl ; CHECK: movd diff --git a/llvm/test/CodeGen/X86/widen_cast-6.ll b/llvm/test/CodeGen/X86/widen_cast-6.ll index 08759bf5510c..39032347c018 100644 --- a/llvm/test/CodeGen/X86/widen_cast-6.ll +++ b/llvm/test/CodeGen/X86/widen_cast-6.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse41 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse41 | FileCheck %s ; CHECK: movd ; Test bit convert that requires widening in the operand. diff --git a/llvm/test/CodeGen/X86/widen_conv-1.ll b/llvm/test/CodeGen/X86/widen_conv-1.ll index a2029dd2748d..f6810cda9e35 100644 --- a/llvm/test/CodeGen/X86/widen_conv-1.ll +++ b/llvm/test/CodeGen/X86/widen_conv-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: pshufd ; CHECK: paddd diff --git a/llvm/test/CodeGen/X86/widen_conv-2.ll b/llvm/test/CodeGen/X86/widen_conv-2.ll index b24a9b36673c..969cb512beb3 100644 --- a/llvm/test/CodeGen/X86/widen_conv-2.ll +++ b/llvm/test/CodeGen/X86/widen_conv-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: movswl ; CHECK: movswl diff --git a/llvm/test/CodeGen/X86/widen_conv-3.ll b/llvm/test/CodeGen/X86/widen_conv-3.ll index 1a40800de975..a25fae9e1bc8 100644 --- a/llvm/test/CodeGen/X86/widen_conv-3.ll +++ b/llvm/test/CodeGen/X86/widen_conv-3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: cvtsi2ss ; sign to float v2i16 to v2f32 diff --git a/llvm/test/CodeGen/X86/widen_conv-4.ll b/llvm/test/CodeGen/X86/widen_conv-4.ll index e505b62a3dbf..80f3a492c494 100644 --- a/llvm/test/CodeGen/X86/widen_conv-4.ll +++ b/llvm/test/CodeGen/X86/widen_conv-4.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; CHECK: cvtsi2ss ; unsigned to float v7i16 to v7f32 diff --git a/llvm/test/CodeGen/X86/widen_extract-1.ll b/llvm/test/CodeGen/X86/widen_extract-1.ll index 308e6b859be6..4bcac58f2b6c 100644 --- a/llvm/test/CodeGen/X86/widen_extract-1.ll +++ b/llvm/test/CodeGen/X86/widen_extract-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+sse42 | FileCheck %s ; widen extract subvector define void @convert(<2 x double>* %dst.addr, <3 x double> %src) { diff --git a/llvm/test/CodeGen/X86/widen_load-1.ll b/llvm/test/CodeGen/X86/widen_load-1.ll index d397645f193f..639617f17774 100644 --- a/llvm/test/CodeGen/X86/widen_load-1.ll +++ b/llvm/test/CodeGen/X86/widen_load-1.ll @@ -1,4 +1,4 @@ -; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -disable-mmx | FileCheck %s +; RUN: llc %s -o - -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; PR4891 ; This load should be before the call, not after. diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll index 551704c498fa..642206316c6b 100644 --- a/llvm/test/CodeGen/X86/widen_load-2.ll +++ b/llvm/test/CodeGen/X86/widen_load-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -o - -march=x86-64 -mattr=+sse42 | FileCheck %s ; Test based on pr5626 to load/store ; diff --git a/llvm/test/CodeGen/X86/widen_shuffle-1.ll b/llvm/test/CodeGen/X86/widen_shuffle-1.ll index 463f522a11df..034c42c758be 100644 --- a/llvm/test/CodeGen/X86/widen_shuffle-1.ll +++ b/llvm/test/CodeGen/X86/widen_shuffle-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s ; widening shuffle v3float and then a add define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {