[VE] (conditional) branch modification & isel patterns
Summary: InstInfo for branch modification, (conditional) branch isel patterns and tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73632
This commit is contained in:
Kazushi (Jam) Marukawa
Simon Moll
parent
b63629a58d
commit
fef80a2946
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@ -44,6 +44,7 @@ public:
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
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bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
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StringRef getPassName() const override {
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@ -55,6 +56,29 @@ public:
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};
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} // end anonymous namespace
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bool VEDAGToDAGISel::SelectADDRrr(SDValue Addr, SDValue &R1, SDValue &R2) {
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if (Addr.getOpcode() == ISD::FrameIndex)
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return false;
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if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress ||
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Addr.getOpcode() == ISD::TargetGlobalTLSAddress)
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return false; // direct calls.
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if (Addr.getOpcode() == ISD::ADD) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
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if (isInt<13>(CN->getSExtValue()))
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return false; // Let the reg+imm pattern catch this!
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if (Addr.getOperand(0).getOpcode() == VEISD::Lo ||
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Addr.getOperand(1).getOpcode() == VEISD::Lo)
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return false; // Let the reg+imm pattern catch this!
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R1 = Addr.getOperand(0);
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R2 = Addr.getOperand(1);
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return true;
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}
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return false; // Let the reg+imm pattern catch this!
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}
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bool VEDAGToDAGISel::SelectADDRri(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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auto AddrTy = Addr->getValueType(0);
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@ -497,8 +497,9 @@ VETargetLowering::VETargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::f32, &VE::F32RegClass);
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addRegisterClass(MVT::f64, &VE::I64RegClass);
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// Custom legalize GlobalAddress nodes into LO/HI parts.
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// Custom legalize address nodes into LO/HI parts.
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MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
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setOperationAction(ISD::BlockAddress, PtrVT, Custom);
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setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
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// VE has no REM or DIVREM operations.
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@ -554,6 +555,10 @@ SDValue VETargetLowering::withTargetFlags(SDValue Op, unsigned TF,
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return DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA),
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GA->getValueType(0), GA->getOffset(), TF);
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if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
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return DAG.getTargetBlockAddress(BA->getBlockAddress(), Op.getValueType(),
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0, TF);
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llvm_unreachable("Unhandled address SDNode");
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}
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@ -594,10 +599,17 @@ SDValue VETargetLowering::LowerGlobalAddress(SDValue Op,
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return makeAddress(Op, DAG);
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}
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SDValue VETargetLowering::LowerBlockAddress(SDValue Op,
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SelectionDAG &DAG) const {
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return makeAddress(Op, DAG);
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}
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SDValue VETargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default:
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llvm_unreachable("Should not custom lower this!");
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case ISD::BlockAddress:
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return LowerBlockAddress(Op, DAG);
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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}
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@ -71,6 +71,7 @@ public:
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/// Custom Lower {
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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/// } Custom Lower
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@ -38,6 +38,243 @@ VEInstrInfo::VEInstrInfo(VESubtarget &ST)
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: VEGenInstrInfo(VE::ADJCALLSTACKDOWN, VE::ADJCALLSTACKUP), RI(),
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Subtarget(ST) {}
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static bool IsIntegerCC(unsigned CC) { return (CC < VECC::CC_AF); }
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static VECC::CondCodes GetOppositeBranchCondition(VECC::CondCodes CC) {
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switch(CC) {
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case VECC::CC_IG: return VECC::CC_ILE;
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case VECC::CC_IL: return VECC::CC_IGE;
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case VECC::CC_INE: return VECC::CC_IEQ;
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case VECC::CC_IEQ: return VECC::CC_INE;
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case VECC::CC_IGE: return VECC::CC_IL;
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case VECC::CC_ILE: return VECC::CC_IG;
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case VECC::CC_AF: return VECC::CC_AT;
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case VECC::CC_G: return VECC::CC_LENAN;
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case VECC::CC_L: return VECC::CC_GENAN;
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case VECC::CC_NE: return VECC::CC_EQNAN;
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case VECC::CC_EQ: return VECC::CC_NENAN;
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case VECC::CC_GE: return VECC::CC_LNAN;
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case VECC::CC_LE: return VECC::CC_GNAN;
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case VECC::CC_NUM: return VECC::CC_NAN;
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case VECC::CC_NAN: return VECC::CC_NUM;
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case VECC::CC_GNAN: return VECC::CC_LE;
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case VECC::CC_LNAN: return VECC::CC_GE;
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case VECC::CC_NENAN: return VECC::CC_EQ;
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case VECC::CC_EQNAN: return VECC::CC_NE;
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case VECC::CC_GENAN: return VECC::CC_L;
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case VECC::CC_LENAN: return VECC::CC_G;
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case VECC::CC_AT: return VECC::CC_AF;
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}
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llvm_unreachable("Invalid cond code");
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}
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// Treat br.l [BCR AT] as unconditional branch
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static bool isUncondBranchOpcode(int Opc) {
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return Opc == VE::BCRLa || Opc == VE::BCRWa ||
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Opc == VE::BCRDa || Opc == VE::BCRSa;
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}
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static bool isCondBranchOpcode(int Opc) {
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return Opc == VE::BCRLrr || Opc == VE::BCRLir ||
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Opc == VE::BCRLrm0 || Opc == VE::BCRLrm1 ||
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Opc == VE::BCRLim0 || Opc == VE::BCRLim1 ||
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Opc == VE::BCRWrr || Opc == VE::BCRWir ||
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Opc == VE::BCRWrm0 || Opc == VE::BCRWrm1 ||
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Opc == VE::BCRWim0 || Opc == VE::BCRWim1 ||
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Opc == VE::BCRDrr || Opc == VE::BCRDir ||
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Opc == VE::BCRDrm0 || Opc == VE::BCRDrm1 ||
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Opc == VE::BCRDim0 || Opc == VE::BCRDim1 ||
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Opc == VE::BCRSrr || Opc == VE::BCRSir ||
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Opc == VE::BCRSrm0 || Opc == VE::BCRSrm1 ||
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Opc == VE::BCRSim0 || Opc == VE::BCRSim1;
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}
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static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm()));
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Cond.push_back(LastInst->getOperand(1));
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Cond.push_back(LastInst->getOperand(2));
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Target = LastInst->getOperand(3).getMBB();
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}
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bool VEInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return false;
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if (!isUnpredicatedTerminator(*I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = &*I;
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unsigned LastOpc = LastInst->getOpcode();
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
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if (isUncondBranchOpcode(LastOpc)) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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if (isCondBranchOpcode(LastOpc)) {
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// Block ends with fall-through condbranch.
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parseCondBranch(LastInst, TBB, Cond);
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return false;
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}
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return true; // Can't handle indirect branch.
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}
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// Get the instruction before it if it is a terminator.
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MachineInstr *SecondLastInst = &*I;
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unsigned SecondLastOpc = SecondLastInst->getOpcode();
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// If AllowModify is true and the block ends with two or more unconditional
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// branches, delete all but the first unconditional branch.
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if (AllowModify && isUncondBranchOpcode(LastOpc)) {
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while (isUncondBranchOpcode(SecondLastOpc)) {
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LastInst->eraseFromParent();
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LastInst = SecondLastInst;
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LastOpc = LastInst->getOpcode();
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if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
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// Return now the only terminator is an unconditional branch.
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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SecondLastInst = &*I;
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SecondLastOpc = SecondLastInst->getOpcode();
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}
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}
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
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return true;
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// If the block ends with a B and a Bcc, handle it.
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if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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parseCondBranch(SecondLastInst, TBB, Cond);
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two unconditional branches, handle it. The second
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// one is not executed.
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if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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return false;
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}
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// TODO ...likewise if it ends with an indirect branch followed by an unconditional
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// branch.
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// if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
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// I = LastInst;
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// if (AllowModify)
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// I->eraseFromParent();
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// return true;
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// }
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// Otherwise, can't handle this.
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return true;
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}
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unsigned VEInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded) const {
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 3 || Cond.size() == 0) &&
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"VE branch conditions should have three component!");
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assert(!BytesAdded && "code size not handled");
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if (Cond.empty()) {
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// Uncondition branch
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(VE::BCRLa))
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.addMBB(TBB);
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return 1;
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}
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// Conditional branch
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// (BCRir CC sy sz addr)
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assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented");
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unsigned opc[2];
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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MachineFunction *MF = MBB.getParent();
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const MachineRegisterInfo &MRI = MF->getRegInfo();
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unsigned Reg = Cond[2].getReg();
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if (IsIntegerCC(Cond[0].getImm())) {
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if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
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opc[0] = VE::BCRWir;
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opc[1] = VE::BCRWrr;
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} else {
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opc[0] = VE::BCRLir;
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opc[1] = VE::BCRLrr;
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}
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} else {
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if (TRI->getRegSizeInBits(Reg, MRI) == 32) {
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opc[0] = VE::BCRSir;
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opc[1] = VE::BCRSrr;
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} else {
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opc[0] = VE::BCRDir;
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opc[1] = VE::BCRDrr;
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}
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}
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if (Cond[1].isImm()) {
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BuildMI(&MBB, DL, get(opc[0]))
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.add(Cond[0]) // condition code
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.add(Cond[1]) // lhs
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.add(Cond[2]) // rhs
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.addMBB(TBB);
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} else {
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BuildMI(&MBB, DL, get(opc[1]))
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.add(Cond[0])
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.add(Cond[1])
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.add(Cond[2])
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.addMBB(TBB);
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}
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if (!FBB)
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return 1;
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BuildMI(&MBB, DL, get(VE::BCRLa))
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.addMBB(FBB);
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return 2;
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}
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unsigned VEInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "code size not handled");
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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if (!isUncondBranchOpcode(I->getOpcode()) &&
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!isCondBranchOpcode(I->getOpcode()))
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break; // Not a branch
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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bool VEInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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VECC::CondCodes CC = static_cast<VECC::CondCodes>(Cond[0].getImm());
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Cond[0].setImm(GetOppositeBranchCondition(CC));
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return false;
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}
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static bool IsAliasOfSX(Register Reg) {
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return VE::I8RegClass.contains(Reg) || VE::I16RegClass.contains(Reg) ||
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VE::I32RegClass.contains(Reg) || VE::I64RegClass.contains(Reg) ||
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@ -37,6 +37,25 @@ public:
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///
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const VERegisterInfo &getRegisterInfo() const { return RI; }
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/// Branch Analysis & Modification {
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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/// } Branch Analysis & Modification
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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@ -131,9 +131,15 @@ def fcond2cc : SDNodeXForm<cond, [{
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}]>;
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// Addressing modes.
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def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
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def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
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// ASX format of memory address
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def MEMrr : Operand<iPTR> {
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let PrintMethod = "printMemASXOperand";
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let MIOperandInfo = (ops ptr_rc, ptr_rc);
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}
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def MEMri : Operand<iPTR> {
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let PrintMethod = "printMemASXOperand";
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let MIOperandInfo = (ops ptr_rc, i64imm);
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@ -539,6 +545,55 @@ multiclass BCRm<string opcStr, string opcStrAt, bits<8> opc,
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let cz = 1;
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let hasSideEffects = 0;
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}
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def ir : CF<
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opc, (outs),
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(ins CCOp:$cf, immOp:$sy, RC:$sz, brtarget32:$imm32),
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!strconcat(opcStr, " $sy, $sz, $imm32")> {
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let cy = 0;
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let cz = 1;
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let hasSideEffects = 0;
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}
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def rm0 : CF<
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opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32),
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!strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> {
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let cy = 1;
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let cz = 0;
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let sz{6} = 1;
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let hasSideEffects = 0;
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}
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def rm1 : CF<
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opc, (outs), (ins CCOp:$cf, RC:$sy, immOp2:$sz, brtarget32:$imm32),
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!strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> {
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let cy = 1;
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let cz = 0;
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let hasSideEffects = 0;
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}
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def im0 : CF<
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opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32),
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!strconcat(opcStr, " $sy, (${sz})0, $imm32"), []> {
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let cy = 0;
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let cz = 0;
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let sz{6} = 1;
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let hasSideEffects = 0;
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}
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def im1 : CF<
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opc, (outs), (ins CCOp:$cf, immOp:$sy, immOp2:$sz, brtarget32:$imm32),
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!strconcat(opcStr, " $sy, (${sz})1, $imm32"), []> {
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let cy = 0;
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let cz = 0;
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let hasSideEffects = 0;
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}
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def a : CF<
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opc, (outs), (ins brtarget32:$imm32),
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!strconcat(opcStrAt, " $imm32"), []> {
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let cy = 0;
|
||||
let sy = 0;
|
||||
let cz = 0;
|
||||
let sz = 0;
|
||||
let cf = 15; /* AT */
|
||||
let isBarrier = 1;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
}
|
||||
|
||||
// Multiclass for floating point conversion instructions.
|
||||
|
|
@ -866,6 +921,39 @@ def ST1Bri : RM<
|
|||
def : Pat<(f64 (load ADDRri:$addr)), (LDSri ADDRri:$addr)>;
|
||||
def : Pat<(store f64:$sx, ADDRri:$addr), (STSri ADDRri:$addr, $sx)>;
|
||||
|
||||
// Control-flow
|
||||
|
||||
// Jump instruction
|
||||
let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cy = 1, cz = 1,
|
||||
isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in
|
||||
def BC : CF<
|
||||
0x19, (outs), (ins CCOp:$cf, I64:$sy, brtarget32:$imm32),
|
||||
"b.${cf}.l $sy, $imm32">;
|
||||
|
||||
// Jump always instruction is treated as a special case of jump in order
|
||||
// to make finding unconditional jump easy.
|
||||
let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0,
|
||||
cz = 1,
|
||||
isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1,
|
||||
hasDelaySlot = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
|
||||
def BArr : CF<
|
||||
0x19, (outs), (ins MEMrr:$addr),
|
||||
"b.l $addr",
|
||||
[(brind ADDRrr:$addr)]>;
|
||||
def BAri : CF<
|
||||
0x19, (outs), (ins MEMri:$addr),
|
||||
"b.l $addr",
|
||||
[(brind ADDRri:$addr)]>;
|
||||
}
|
||||
|
||||
// Jump never instruction is also a special case of jump.
|
||||
let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 0 /* AF */, cy = 1, sy = 0,
|
||||
cz = 1,
|
||||
isBranch = 1, isTerminator = 1, hasDelaySlot = 1, hasSideEffects = 0 in
|
||||
def BN : CF<
|
||||
0x19, (outs), (ins brtarget32:$imm32),
|
||||
"b.af.l $imm32">;
|
||||
|
||||
// Return instruction is also a special case of jump.
|
||||
let cx = 0, cx2 = 0, bpf = 0 /* NONE */, cf = 15 /* AT */, cy = 0, sy = 0,
|
||||
cz = 1, sz = 0x10 /* SX10 */, imm32 = 0, Uses = [SX10],
|
||||
|
|
@ -879,6 +967,12 @@ def RET : CF<
|
|||
// Branch instruction
|
||||
let cx = 0, cx2 = 0, bpf = 0 /* NONE */ in
|
||||
defm BCRL : BCRm<"br${cf}.l", "br.l", 0x18, I64, i64, simm7Op64, uimm6Op64>;
|
||||
let cx = 1, cx2 = 0, bpf = 0 /* NONE */ in
|
||||
defm BCRW : BCRm<"br${cf}.w", "br.w", 0x18, I32, i32, simm7Op32, uimm6Op32>;
|
||||
let cx = 0, cx2 = 1, bpf = 0 /* NONE */ in
|
||||
defm BCRD : BCRm<"br${cf}.d", "br.d", 0x18, I64, f64, simm7Op64, uimm6Op64>;
|
||||
let cx = 1, cx2 = 1, bpf = 0 /* NONE */ in
|
||||
defm BCRS : BCRm<"br${cf}.s", "br.s", 0x18, F32, f32, simm7Op32, uimm6Op32>;
|
||||
|
||||
let cx = 0, cy = 0, cz = 1, hasSideEffects = 0 in {
|
||||
let sy = 3 in
|
||||
|
|
@ -1041,6 +1135,22 @@ def : Pat<(call tglobaladdr:$dst),
|
|||
def : Pat<(call i64:$dst),
|
||||
(CALLr i64:$dst)>;
|
||||
|
||||
// Branches
|
||||
def : Pat<(br bb:$addr), (BCRLa bb:$addr)>;
|
||||
|
||||
// brcc
|
||||
def : Pat<(brcc CCSIOp:$cond, i32:$l, i32:$r, bb:$addr),
|
||||
(BCRWrr (icond2cc $cond), $l, $r, bb:$addr)>;
|
||||
def : Pat<(brcc CCUIOp:$cond, i32:$l, i32:$r, bb:$addr),
|
||||
(BCRWir (icond2cc $cond), 0, (CMPUWrr $r, $l), bb:$addr)>;
|
||||
def : Pat<(brcc CCSIOp:$cond, i64:$l, i64:$r, bb:$addr),
|
||||
(BCRLrr (icond2cc $cond), $l, $r, bb:$addr)>;
|
||||
def : Pat<(brcc CCUIOp:$cond, i64:$l, i64:$r, bb:$addr),
|
||||
(BCRLir (icond2cc $cond), 0, (CMPrr $r, $l), bb:$addr)>;
|
||||
def : Pat<(brcc cond:$cond, f32:$l, f32:$r, bb:$addr),
|
||||
(BCRSrr (fcond2cc $cond), $l, $r, bb:$addr)>;
|
||||
def : Pat<(brcc cond:$cond, f64:$l, f64:$r, bb:$addr),
|
||||
(BCRDrr (fcond2cc $cond), $l, $r, bb:$addr)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Pseudo Instructions
|
||||
|
|
|
|||
|
|
@ -0,0 +1,290 @@
|
|||
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
|
||||
|
||||
define signext i8 @func1(i8 signext %a, i8 signext %b) {
|
||||
; CHECK-LABEL: func1:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brle.w %s0, %s1, .LBB0_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB0_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: sla.w.sx %s0, %s0, 24
|
||||
; CHECK-NEXT: sra.w.sx %s0, %s0, 24
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp sgt i8 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
%r8 = trunc i32 %ret.val to i8
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i8 [ %r8, %on.true ], [ 0, %entry ]
|
||||
ret i8 %r
|
||||
}
|
||||
|
||||
declare i32 @ret(i32)
|
||||
|
||||
define i32 @func2(i16 signext %a, i16 signext %b) {
|
||||
; CHECK-LABEL: func2:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brle.w %s0, %s1, .LBB1_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB1_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp sgt i16 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func3(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: func3:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brle.w %s0, %s1, .LBB2_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB2_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp sgt i32 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func4(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: func4:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brle.l %s0, %s1, .LBB3_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB3_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func5(i8 zeroext %a, i8 zeroext %b) {
|
||||
; CHECK-LABEL: func5:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
|
||||
; CHECK-NEXT: brle.w 0, %s0, .LBB4_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB4_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp ugt i8 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func6(i16 zeroext %a, i16 zeroext %b) {
|
||||
; CHECK-LABEL: func6:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
|
||||
; CHECK-NEXT: brle.w 0, %s0, .LBB5_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB5_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp ugt i16 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func7(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: func7:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: cmpu.w %s0, %s1, %s0
|
||||
; CHECK-NEXT: brle.w 0, %s0, .LBB6_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB6_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = icmp ugt i32 %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func8(float %a, float %b) {
|
||||
; CHECK-LABEL: func8:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brlenan.s %s0, %s1, .LBB7_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB7_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = fcmp ogt float %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func9(double %a, double %b) {
|
||||
; CHECK-LABEL: func9:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: brlenan.d %s0, %s1, .LBB8_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB8_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = fcmp ogt double %a, %b
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
define i32 @func10(double %a, double %b) {
|
||||
; CHECK-LABEL: func10:
|
||||
; CHECK: .LBB{{[0-9]+}}_5:
|
||||
; CHECK-NEXT: lea.sl %s1, 1075052544
|
||||
; CHECK-NEXT: brlenan.d %s0, %s1, .LBB9_1
|
||||
; CHECK-NEXT: # %bb.2:
|
||||
; CHECK-NEXT: lea %s0, ret@lo
|
||||
; CHECK-NEXT: and %s0, %s0, (32)0
|
||||
; CHECK-NEXT: lea.sl %s12, ret@hi(%s0)
|
||||
; CHECK-NEXT: or %s0, 2, (0)1
|
||||
; CHECK-NEXT: bsic %lr, (,%s12)
|
||||
; CHECK-NEXT: br.l .LBB9_3
|
||||
; CHECK: .LBB{{[0-9]+}}_1:
|
||||
; CHECK-NEXT: or %s0, 0, (0)1
|
||||
; CHECK: .LBB{{[0-9]+}}_3:
|
||||
; CHECK-NEXT: or %s11, 0, %s9
|
||||
entry:
|
||||
%cmp = fcmp ogt double %a, 5.000000e+00
|
||||
br i1 %cmp, label %on.true, label %join
|
||||
|
||||
on.true:
|
||||
%ret.val = tail call i32 @ret(i32 2)
|
||||
br label %join
|
||||
|
||||
join:
|
||||
%r = phi i32 [ %ret.val, %on.true ], [ 0, %entry ]
|
||||
ret i32 %r
|
||||
}
|
||||
Loading…
Reference in New Issue