Rewrite ISD::FCOPYSIGN lowering to never use i64. Not really ideal, but
it's late, and I don't have any better ideas at the moment. Fixes PR4257. llvm-svn: 72363
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@ -3142,36 +3142,27 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
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break;
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break;
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case TargetLowering::Legal: break;
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case TargetLowering::Legal: break;
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case TargetLowering::Expand: {
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case TargetLowering::Expand: {
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// If this target supports fabs/fneg natively and select is cheap,
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assert((Tmp2.getValueType() == MVT::f32 ||
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// do this efficiently.
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Tmp2.getValueType() == MVT::f64) && isTypeLegal(MVT::i32) &&
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if (!TLI.isSelectExpensive() &&
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"Ugly special-cased code!");
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TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
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// Get the sign bit of the RHS.
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TargetLowering::Legal &&
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SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
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TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
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SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, NULL,
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TargetLowering::Legal) {
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0);
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// Get the sign bit of the RHS.
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if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
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MVT IVT =
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StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
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Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
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StackPtr, DAG.getIntPtrConstant(4));
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SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
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SDValue SignBit = DAG.getLoad(MVT::i32, dl, Ch, StackPtr, NULL, 0);
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SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
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SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i32),
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SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
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SignBit, DAG.getConstant(0, MVT::i32), ISD::SETLT);
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// Get the absolute value of the result.
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// Get the absolute value of the result.
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SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
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SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
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// Select between the nabs and abs value based on the sign bit of
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// Select between the nabs and abs value based on the sign bit of
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// the input.
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// the input.
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Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
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Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
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DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
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DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
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AbsVal),
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AbsVal),
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AbsVal);
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AbsVal);
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Result = LegalizeOp(Result);
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break;
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}
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// Otherwise, do bitwise ops!
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MVT NVT =
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Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
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Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
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Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
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Result = LegalizeOp(Result);
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Result = LegalizeOp(Result);
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break;
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break;
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}
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}
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