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[mips][msa] Direct Object Emission support for LD/ST instructions. 

llvm-svn: 193082
This commit is contained in:
Matheus Almeida 2013-10-21 13:07:13 +00:00
parent 8ddad15177
commit fe0bf9f618
4 changed files with 86 additions and 24 deletions
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19
llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
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@ -210,6 +210,9 @@ static DecodeStatus DecodeMem(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@ -530,6 +533,22 @@ static DecodeStatus DecodeMem(MCInst &Inst,
return MCDisassembler::Success;
}
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
unsigned Base = fieldFromInstruction(Insn, 11, 5);
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,

11
llvm/lib/Target/Mips/MipsMSAInstrFormats.td
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@ -341,6 +341,17 @@ class MSA_I10_FMT<bits<3> major, bits<2> df, bits<6> minor>: MSAInst {
let Inst{5-0} = minor;
}
class MSA_MI10_FMT<bits<2> df, bits<4> minor>: MSAInst {
bits<21> addr;
bits<5> wd;
let Inst{25-16} = addr{9-0};
let Inst{15-11} = addr{20-16};
let Inst{10-6} = wd;
let Inst{5-2} = minor;
let Inst{1-0} = df;
}
class MSA_VEC_FMT<bits<5> major, bits<6> minor>: MSAInst {
bits<5> wt;
bits<5> ws;

50
llvm/lib/Target/Mips/MipsMSAInstrInfo.td
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@ -758,10 +758,10 @@ class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
class LD_B_ENC : MSA_I5_FMT<0b110, 0b00, 0b000111>;
class LD_H_ENC : MSA_I5_FMT<0b110, 0b01, 0b000111>;
class LD_W_ENC : MSA_I5_FMT<0b110, 0b10, 0b000111>;
class LD_D_ENC : MSA_I5_FMT<0b110, 0b11, 0b000111>;
class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
class LDI_B_ENC : MSA_I10_FMT<0b010, 0b00, 0b001100>;
class LDI_H_ENC : MSA_I10_FMT<0b010, 0b01, 0b001100>;
@ -982,10 +982,10 @@ class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
class ST_B_ENC : MSA_I5_FMT<0b111, 0b00, 0b000111>;
class ST_H_ENC : MSA_I5_FMT<0b111, 0b01, 0b000111>;
class ST_W_ENC : MSA_I5_FMT<0b111, 0b10, 0b000111>;
class ST_D_ENC : MSA_I5_FMT<0b111, 0b11, 0b000111>;
class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
@ -2037,20 +2037,21 @@ class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
MSA128DOpnd>;
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem,
ComplexPattern Addr = addrRegImm,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs RCWD:$wd);
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
list<dag> Pattern = [(set RCWD:$wd, (TyNode (OpNode Addr:$addr)))];
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128B>;
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128H>;
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128W>;
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128D>;
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
@ -2364,20 +2365,21 @@ class SRLRI_D_DESC : MSA_BIT_D_DESC_BASE<"srlri.d", int_mips_srlri_d,
MSA128DOpnd>;
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem,
ComplexPattern Addr = addrRegImm,
ValueType TyNode, RegisterOperand ROWD,
Operand MemOpnd = mem, ComplexPattern Addr = addrRegImm,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs);
dag InOperandList = (ins RCWD:$wd, MemOpnd:$addr);
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
list<dag> Pattern = [(OpNode (TyNode RCWD:$wd), Addr:$addr)];
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
InstrItinClass Itinerary = itin;
string DecoderMethod = "DecodeMSA128Mem";
}
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128B>;
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128H>;
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128W>;
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128D>;
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
MSA128BOpnd>;

30
llvm/test/MC/Mips/msa/test_mi10.s Normal file
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@ -0,0 +1,30 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
#
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
#
# CHECK: ld.b $w2, 1($7) # encoding: [0x78,0x01,0x38,0xa0]
# CHECK: ld.h $w16, -9($zero) # encoding: [0x7b,0xf7,0x04,0x21]
# CHECK: ld.w $w13, -6($4) # encoding: [0x7b,0xfa,0x23,0x62]
# CHECK: ld.d $w1, -5($16) # encoding: [0x7b,0xfb,0x80,0x63]
# CHECK: st.b $w29, 1($14) # encoding: [0x78,0x01,0x77,0x64]
# CHECK: st.h $w6, -1($8) # encoding: [0x7b,0xff,0x41,0xa5]
# CHECK: st.w $w18, 8($15) # encoding: [0x78,0x08,0x7c,0xa6]
# CHECK: st.d $w3, -14($18) # encoding: [0x7b,0xf2,0x90,0xe7]
# CHECKOBJDUMP: ld.b $w2, 1($7)
# CHECKOBJDUMP: ld.h $w16, -9($zero)
# CHECKOBJDUMP: ld.w $w13, -6($4)
# CHECKOBJDUMP: ld.d $w1, -5($16)
# CHECKOBJDUMP: st.b $w29, 1($14)
# CHECKOBJDUMP: st.h $w6, -1($8)
# CHECKOBJDUMP: st.w $w18, 8($15)
# CHECKOBJDUMP: st.d $w3, -14($18)
ld.b $w2, 1($7)
ld.h $w16, -9($zero)
ld.w $w13, -6($4)
ld.d $w1, -5($16)
st.b $w29, 1($14)
st.h $w6, -1($8)
st.w $w18, 8($15)
st.d $w3, -14($18)