Revert "RegScavenging: Add scavengeRegisterBackwards()"
The ppc64 multistage bot fails on this. This reverts commit r279124. Also Revert "CodeGen: Add/Factor out LiveRegUnits class; NFCI" because it depends on the previous change This reverts commit r279171. llvm-svn: 279199
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@ -1,116 +0,0 @@
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//===- llvm/CodeGen/LiveRegUnits.h - Register Unit Set ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// A set of register units. It is intended for register liveness tracking.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEREGUNITS_H
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#define LLVM_CODEGEN_LIVEREGUNITS_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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namespace llvm {
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class MachineInstr;
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class MachineBasicBlock;
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/// A set of register units used to track register liveness.
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class LiveRegUnits {
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const TargetRegisterInfo *TRI;
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BitVector Units;
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public:
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/// Constructs a new empty LiveRegUnits set.
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LiveRegUnits() : TRI(nullptr) {}
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/// Constructs and initialize an empty LiveRegUnits set.
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LiveRegUnits(const TargetRegisterInfo &TRI) {
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init(TRI);
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}
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/// Initialize and clear the set.
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void init(const TargetRegisterInfo &TRI) {
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this->TRI = &TRI;
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Units.reset();
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Units.resize(TRI.getNumRegUnits());
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}
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/// Clears the set.
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void clear() { Units.reset(); }
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/// Returns true if the set is empty.
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bool empty() const { return Units.empty(); }
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/// Adds register units covered by physical register \p Reg.
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void addReg(unsigned Reg) {
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for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
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Units.set(*Unit);
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}
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/// \brief Adds register units covered by physical register \p Reg that are
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/// part of the lanemask \p Mask.
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void addRegMasked(unsigned Reg, LaneBitmask Mask) {
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for (MCRegUnitMaskIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
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LaneBitmask UnitMask = (*Unit).second;
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if (UnitMask == 0 || (UnitMask & Mask) != 0)
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Units.set((*Unit).first);
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}
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}
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/// Removes all register units covered by physical register \p Reg.
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void removeReg(unsigned Reg) {
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for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit)
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Units.reset(*Unit);
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}
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/// Removes register units not preserved by the regmask \p RegMask.
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/// The regmask has the same format as the one in the RegMask machine operand.
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void removeRegsNotPreserved(const uint32_t *RegMask);
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/// Returns true if no part of physical register \p Reg is live.
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bool available(unsigned Reg) const {
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for (MCRegUnitIterator Unit(Reg, TRI); Unit.isValid(); ++Unit) {
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if (Units.test(*Unit))
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return false;
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}
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return true;
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}
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/// Updates liveness when stepping backwards over the instruction \p MI.
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void stepBackward(const MachineInstr &MI);
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/// Adds registers living out of block \p MBB.
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/// Live out registers are the union of the live-in registers of the successor
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/// blocks and pristine registers. Live out registers of the end block are the
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/// callee saved registers.
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void addLiveOuts(const MachineBasicBlock &MBB);
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/// Adds registers living into block \p MBB.
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void addLiveIns(const MachineBasicBlock &MBB);
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/// Adds all register units marked in the bitvector \p RegUnits.
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void addUnits(const BitVector &RegUnits) {
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Units |= RegUnits;
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}
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/// Removes all register units marked in the bitvector \p RegUnits.
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void removeUnits(const BitVector &RegUnits) {
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Units.reset(RegUnits);
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}
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/// Return the internal bitvector representation of the set.
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const BitVector &getBitVector() const {
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return Units;
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}
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};
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} // namespace llvm
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#endif
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@ -19,7 +19,6 @@
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#define LLVM_CODEGEN_REGISTERSCAVENGING_H
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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@ -59,7 +58,10 @@ class RegScavenger {
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/// A vector of information on scavenged registers.
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SmallVector<ScavengedInfo, 2> Scavenged;
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LiveRegUnits LiveUnits;
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/// The current state of each reg unit immediately before MBBI.
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/// One bit per register unit. If bit is not set it means any
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/// register containing that register unit is currently being used.
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BitVector RegUnitsAvailable;
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// These BitVectors are only used internally to forward(). They are members
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// to avoid frequent reallocations.
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@ -155,24 +157,12 @@ public:
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/// available and do the appropriate bookkeeping. SPAdj is the stack
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/// adjustment due to call frame, it's passed along to eliminateFrameIndex().
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/// Returns the scavenged register.
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/// This function performs worse if kill flags are incomplete, consider using
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/// scavengeRegisterBackwards() instead!
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unsigned scavengeRegister(const TargetRegisterClass *RegClass,
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MachineBasicBlock::iterator I, int SPAdj);
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unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
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return scavengeRegister(RegClass, MBBI, SPAdj);
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}
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/// Make a register of the specific register class available from the current
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/// position backwards to the place before \p To. If \p RestoreAfter is true
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/// this includes the instruction following the current position.
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/// SPAdj is the stack adjustment due to call frame, it's passed along to
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/// eliminateFrameIndex().
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/// Returns the scavenged register.
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unsigned scavengeRegisterBackwards(const TargetRegisterClass &RC,
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MachineBasicBlock::iterator To,
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bool RestoreAfter, int SPAdj);
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/// Tell the scavenger a register is used.
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void setRegUsed(unsigned Reg, LaneBitmask LaneMask = ~0u);
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private:
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/// setUsed / setUnused - Mark the state of one or a number of register units.
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///
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void setUsed(const BitVector &RegUnits) {
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LiveUnits.addUnits(RegUnits);
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void setUsed(BitVector &RegUnits) {
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RegUnitsAvailable.reset(RegUnits);
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}
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void setUnused(const BitVector &RegUnits) {
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LiveUnits.removeUnits(RegUnits);
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void setUnused(BitVector &RegUnits) {
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RegUnitsAvailable |= RegUnits;
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}
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/// Processes the current instruction and fill the KillRegUnits and
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/// Mark live-in registers of basic block as used.
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void setLiveInsUsed(const MachineBasicBlock &MBB);
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/// Spill a register after position \p After and reload it before position
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/// \p UseMI.
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ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
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MachineBasicBlock::iterator After,
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MachineBasicBlock::iterator &UseMI);
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};
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} // End llvm namespace
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@ -44,7 +44,6 @@ add_llvm_library(LLVMCodeGen
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LiveRangeCalc.cpp
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LiveRangeEdit.cpp
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LiveRegMatrix.cpp
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LiveRegUnits.cpp
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LiveStackAnalysis.cpp
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LiveVariables.cpp
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LLVMTargetMachine.cpp
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@ -1,97 +0,0 @@
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//===--- LiveRegUnits.cpp - Register Unit Set -----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file imlements the LiveRegUnits set.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/LiveRegUnits.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBundle.h"
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using namespace llvm;
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void LiveRegUnits::removeRegsNotPreserved(const uint32_t *RegMask) {
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for (unsigned U = 0, E = TRI->getNumRegUnits(); U != E; ++U) {
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for (MCRegUnitRootIterator RootReg(U, TRI); RootReg.isValid(); ++RootReg) {
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if (MachineOperand::clobbersPhysReg(RegMask, *RootReg))
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Units.reset(U);
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}
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}
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}
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void LiveRegUnits::stepBackward(const MachineInstr &MI) {
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// Remove defined registers and regmask kills from the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (O->isReg()) {
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if (!O->isDef())
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continue;
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unsigned Reg = O->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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removeReg(Reg);
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} else if (O->isRegMask())
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removeRegsNotPreserved(O->getRegMask());
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}
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// Add uses to the set.
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for (ConstMIBundleOperands O(MI); O.isValid(); ++O) {
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if (!O->isReg() || !O->readsReg())
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continue;
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unsigned Reg = O->getReg();
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if (!TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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addReg(Reg);
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}
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}
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/// Add live-in registers of basic block \p MBB to \p LiveUnits.
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static void addLiveIns(LiveRegUnits &LiveUnits, const MachineBasicBlock &MBB) {
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for (const auto &LI : MBB.liveins())
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LiveUnits.addRegMasked(LI.PhysReg, LI.LaneMask);
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}
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static void addLiveOuts(LiveRegUnits &LiveUnits, const MachineBasicBlock &MBB) {
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// To get the live-outs we simply merge the live-ins of all successors.
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for (const MachineBasicBlock *Succ : MBB.successors())
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addLiveIns(LiveUnits, *Succ);
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}
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/// Add pristine registers to the given \p LiveUnits. This function removes
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/// actually saved callee save registers when \p InPrologueEpilogue is false.
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static void removeSavedRegs(LiveRegUnits &LiveUnits, const MachineFunction &MF,
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const MachineFrameInfo &MFI,
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const TargetRegisterInfo &TRI) {
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for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
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LiveUnits.removeReg(Info.getReg());
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}
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void LiveRegUnits::addLiveOuts(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (MFI.isCalleeSavedInfoValid()) {
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for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)
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addReg(*I);
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if (!MBB.isReturnBlock())
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removeSavedRegs(*this, MF, MFI, *TRI);
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}
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::addLiveOuts(*this, MBB);
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}
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void LiveRegUnits::addLiveIns(const MachineBasicBlock &MBB) {
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const MachineFunction &MF = *MBB.getParent();
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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if (MFI.isCalleeSavedInfoValid()) {
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for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I)
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addReg(*I);
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if (&MBB != &MF.front())
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removeSavedRegs(*this, MF, MFI, *TRI);
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}
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::addLiveIns(*this, MBB);
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}
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <algorithm>
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#include <climits>
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using namespace llvm;
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}
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}
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/// Allocate a register for the virtual register \p VReg. The last use of
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/// \p VReg is around the current position of the register scavenger \p RS.
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/// \p ReserveAfter controls whether the scavenged register needs to be reserved
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/// after the current instruction, otherwise it will only be reserved before the
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/// current instruction.
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static unsigned scavengeVReg(MachineRegisterInfo &MRI, RegScavenger &RS,
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unsigned VReg, bool ReserveAfter) {
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#ifndef NDEBUG
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// Verify that all definitions and uses are in the same basic block.
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const MachineBasicBlock *CommonMBB = nullptr;
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bool HadDef = false;
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for (MachineOperand &MO : MRI.reg_nodbg_operands(VReg)) {
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MachineBasicBlock *MBB = MO.getParent()->getParent();
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if (CommonMBB == nullptr)
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CommonMBB = MBB;
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assert(MBB == CommonMBB && "All defs+uses must be in the same basic block");
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if (MO.isDef())
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HadDef = true;
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}
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assert(HadDef && "Must have at least 1 Def");
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#endif
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// We should only have one definition of the register. However to accomodate
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// the requirements of two address code we also allow definitions in
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// subsequent instructions provided they also read the register. That way
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// we get a single contiguous lifetime.
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//
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// Definitions in MRI.def_begin() are unordered, search for the first.
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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MachineRegisterInfo::def_iterator FirstDef =
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std::find_if(MRI.def_begin(VReg), MRI.def_end(),
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[VReg, &TRI](const MachineOperand &MO) {
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return !MO.getParent()->readsRegister(VReg, &TRI);
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});
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assert(FirstDef != MRI.def_end() &&
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"Must have one definition that does not redefine vreg");
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MachineInstr &DefMI = *FirstDef->getParent();
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// The register scavenger will report a free register inserting an emergency
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// spill/reload if necessary.
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int SPAdj = 0;
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const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
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unsigned SReg = RS.scavengeRegisterBackwards(RC, DefMI.getIterator(),
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ReserveAfter, SPAdj);
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MRI.replaceRegWith(VReg, SReg);
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++NumScavengedRegs;
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return SReg;
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}
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/// doScavengeFrameVirtualRegs - Replace all frame index virtual registers
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/// with physical registers. Use the register scavenger to find an
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/// appropriate register to use.
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doScavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger *RS) {
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// Run through the instructions and find any virtual registers.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
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for (MachineBasicBlock &MBB : MF) {
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RS->enterBasicBlockEnd(MBB);
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RS->enterBasicBlock(MBB);
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bool LastIterationHadVRegUses = false;
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for (MachineBasicBlock::iterator I = MBB.end(); I != MBB.begin(); ) {
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--I;
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// Move RegScavenger to the position between *I and *std::next(I).
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RS->backward(I);
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int SPAdj = 0;
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// Look for unassigned vregs in the uses of *std::next(I).
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if (LastIterationHadVRegUses) {
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MachineBasicBlock::iterator N = std::next(I);
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const MachineInstr &NMI = *N;
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for (const MachineOperand &MO : NMI.operands()) {
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if (!MO.isReg() || !MO.readsReg())
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continue;
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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unsigned SReg = scavengeVReg(MRI, *RS, Reg, true);
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N->addRegisterKilled(SReg, &TRI, false);
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RS->setRegUsed(SReg);
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}
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}
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}
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// The instruction stream may change in the loop, so check MBB.end()
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// directly.
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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// We might end up here again with a NULL iterator if we scavenged a
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// register for which we inserted spill code for definition by what was
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// originally the first instruction in MBB.
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if (I == MachineBasicBlock::iterator(nullptr))
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I = MBB.begin();
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// Look for unassigned vregs in the defs of *I.
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LastIterationHadVRegUses = false;
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const MachineInstr &MI = *I;
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MachineBasicBlock::iterator J = std::next(I);
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MachineBasicBlock::iterator P =
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I == MBB.begin() ? MachineBasicBlock::iterator(nullptr)
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: std::prev(I);
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// RS should process this instruction before we might scavenge at this
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// location. This is because we might be replacing a virtual register
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// defined by this instruction, and if so, registers killed by this
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// instruction are available, and defined registers are not.
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RS->forward(I);
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!TargetRegisterInfo::isVirtualRegister(Reg))
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continue;
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// We have to look at all operands anyway so we can precalculate here
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// whether there is a reading operand. This allows use to skip the use
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// step in the next iteration if there was none.
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if (MO.readsReg())
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LastIterationHadVRegUses = true;
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if (MO.isDef()) {
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unsigned SReg = scavengeVReg(MRI, *RS, Reg, false);
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I->addRegisterDead(SReg, &TRI, false);
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}
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// When we first encounter a new virtual register, it
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// must be a definition.
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assert(MO.isDef() && "frame index virtual missing def!");
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// Scavenge a new scratch register
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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unsigned ScratchReg = RS->scavengeRegister(RC, J, SPAdj);
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++NumScavengedRegs;
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// Replace this reference to the virtual register with the
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// scratch register.
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assert(ScratchReg && "Missing scratch register!");
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MRI.replaceRegWith(Reg, ScratchReg);
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|
||||
// Because this instruction was processed by the RS before this
|
||||
// register was allocated, make sure that the RS now records the
|
||||
// register as being used.
|
||||
RS->setRegUsed(ScratchReg);
|
||||
}
|
||||
|
||||
// If the scavenger needed to use one of its spill slots, the
|
||||
// spill code will have been inserted in between I and J. This is a
|
||||
// problem because we need the spill code before I: Move I to just
|
||||
// prior to J.
|
||||
if (I != std::prev(J)) {
|
||||
MBB.splice(J, &MBB, I);
|
||||
|
||||
// Before we move I, we need to prepare the RS to visit I again.
|
||||
// Specifically, RS will assert if it sees uses of registers that
|
||||
// it believes are undefined. Because we have already processed
|
||||
// register kills in I, when it visits I again, it will believe that
|
||||
// those registers are undefined. To avoid this situation, unprocess
|
||||
// the instruction I.
|
||||
assert(RS->getCurrentPosition() == I &&
|
||||
"The register scavenger has an unexpected position");
|
||||
I = P;
|
||||
RS->unprocess(P);
|
||||
} else
|
||||
++I;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -32,7 +32,11 @@ using namespace llvm;
|
|||
#define DEBUG_TYPE "reg-scavenging"
|
||||
|
||||
void RegScavenger::setRegUsed(unsigned Reg, LaneBitmask LaneMask) {
|
||||
LiveUnits.addRegMasked(Reg, LaneMask);
|
||||
for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
|
||||
LaneBitmask UnitMask = (*RUI).second;
|
||||
if (UnitMask == 0 || (LaneMask & UnitMask) != 0)
|
||||
RegUnitsAvailable.reset((*RUI).first);
|
||||
}
|
||||
}
|
||||
|
||||
void RegScavenger::init(MachineBasicBlock &MBB) {
|
||||
|
@ -40,7 +44,6 @@ void RegScavenger::init(MachineBasicBlock &MBB) {
|
|||
TII = MF.getSubtarget().getInstrInfo();
|
||||
TRI = MF.getSubtarget().getRegisterInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
LiveUnits.init(*TRI);
|
||||
|
||||
assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
|
||||
"Target changed?");
|
||||
|
@ -53,6 +56,7 @@ void RegScavenger::init(MachineBasicBlock &MBB) {
|
|||
// Self-initialize.
|
||||
if (!this->MBB) {
|
||||
NumRegUnits = TRI->getNumRegUnits();
|
||||
RegUnitsAvailable.resize(NumRegUnits);
|
||||
KillRegUnits.resize(NumRegUnits);
|
||||
DefRegUnits.resize(NumRegUnits);
|
||||
TmpRegUnits.resize(NumRegUnits);
|
||||
|
@ -65,17 +69,32 @@ void RegScavenger::init(MachineBasicBlock &MBB) {
|
|||
I->Restore = nullptr;
|
||||
}
|
||||
|
||||
// All register units start out unused.
|
||||
RegUnitsAvailable.set();
|
||||
|
||||
// Pristine CSRs are not available.
|
||||
BitVector PR = MF.getFrameInfo().getPristineRegs(MF);
|
||||
for (int I = PR.find_first(); I>0; I = PR.find_next(I))
|
||||
setRegUsed(I);
|
||||
|
||||
Tracking = false;
|
||||
}
|
||||
|
||||
void RegScavenger::setLiveInsUsed(const MachineBasicBlock &MBB) {
|
||||
for (const auto &LI : MBB.liveins())
|
||||
setRegUsed(LI.PhysReg, LI.LaneMask);
|
||||
}
|
||||
|
||||
void RegScavenger::enterBasicBlock(MachineBasicBlock &MBB) {
|
||||
init(MBB);
|
||||
LiveUnits.addLiveIns(MBB);
|
||||
setLiveInsUsed(MBB);
|
||||
}
|
||||
|
||||
void RegScavenger::enterBasicBlockEnd(MachineBasicBlock &MBB) {
|
||||
init(MBB);
|
||||
LiveUnits.addLiveOuts(MBB);
|
||||
// Merge live-ins of successors to get live-outs.
|
||||
for (const MachineBasicBlock *Succ : MBB.successors())
|
||||
setLiveInsUsed(*Succ);
|
||||
|
||||
// Move internal iterator at the last instruction of the block.
|
||||
if (MBB.begin() != MBB.end()) {
|
||||
|
@ -249,13 +268,34 @@ void RegScavenger::backward() {
|
|||
assert(Tracking && "Must be tracking to determine kills and defs");
|
||||
|
||||
const MachineInstr &MI = *MBBI;
|
||||
LiveUnits.stepBackward(MI);
|
||||
|
||||
// Expire scavenge spill frameindex uses.
|
||||
for (ScavengedInfo &I : Scavenged) {
|
||||
if (I.Restore == &MI) {
|
||||
I.Reg = 0;
|
||||
I.Restore = nullptr;
|
||||
// Defined or clobbered registers are available now.
|
||||
for (const MachineOperand &MO : MI.operands()) {
|
||||
if (MO.isRegMask()) {
|
||||
for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd;
|
||||
++RU) {
|
||||
for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
|
||||
if (MO.clobbersPhysReg(*RURI)) {
|
||||
RegUnitsAvailable.set(RU);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (MO.isReg() && MO.isDef()) {
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
|
||||
isReserved(Reg))
|
||||
continue;
|
||||
addRegUnits(RegUnitsAvailable, Reg);
|
||||
}
|
||||
}
|
||||
// Mark read registers as unavailable.
|
||||
for (const MachineOperand &MO : MI.uses()) {
|
||||
if (MO.isReg() && MO.readsReg()) {
|
||||
unsigned Reg = MO.getReg();
|
||||
if (!Reg || TargetRegisterInfo::isVirtualRegister(Reg) ||
|
||||
isReserved(Reg))
|
||||
continue;
|
||||
removeRegUnits(RegUnitsAvailable, Reg);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -267,9 +307,12 @@ void RegScavenger::backward() {
|
|||
}
|
||||
|
||||
bool RegScavenger::isRegUsed(unsigned Reg, bool includeReserved) const {
|
||||
if (isReserved(Reg))
|
||||
return includeReserved;
|
||||
return !LiveUnits.available(Reg);
|
||||
if (includeReserved && isReserved(Reg))
|
||||
return true;
|
||||
for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
|
||||
if (!RegUnitsAvailable.test(*RUI))
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
|
||||
|
@ -355,69 +398,6 @@ unsigned RegScavenger::findSurvivorReg(MachineBasicBlock::iterator StartMI,
|
|||
return Survivor;
|
||||
}
|
||||
|
||||
static std::pair<unsigned, MachineBasicBlock::iterator>
|
||||
findSurvivorBackwards(const TargetRegisterInfo &TRI,
|
||||
MachineBasicBlock::iterator From, MachineBasicBlock::iterator To,
|
||||
BitVector &Available, BitVector &Candidates) {
|
||||
bool FoundTo = false;
|
||||
unsigned Survivor = 0;
|
||||
MachineBasicBlock::iterator Pos;
|
||||
MachineBasicBlock &MBB = *From->getParent();
|
||||
unsigned InstrLimit = 25;
|
||||
unsigned InstrCountDown = InstrLimit;
|
||||
for (MachineBasicBlock::iterator I = From;; --I) {
|
||||
const MachineInstr &MI = *I;
|
||||
|
||||
// Remove any candidates touched by instruction.
|
||||
bool FoundVReg = false;
|
||||
for (const MachineOperand &MO : MI.operands()) {
|
||||
if (MO.isRegMask()) {
|
||||
Candidates.clearBitsNotInMask(MO.getRegMask());
|
||||
continue;
|
||||
}
|
||||
if (!MO.isReg() || MO.isUndef() || MO.isDebug())
|
||||
continue;
|
||||
unsigned Reg = MO.getReg();
|
||||
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
||||
FoundVReg = true;
|
||||
} else if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
||||
for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI)
|
||||
Candidates.reset(*AI);
|
||||
}
|
||||
}
|
||||
|
||||
if (I == To) {
|
||||
// If one of the available registers survived this long take it.
|
||||
Available &= Candidates;
|
||||
int Reg = Available.find_first();
|
||||
if (Reg != -1)
|
||||
return std::make_pair(Reg, MBB.end());
|
||||
// Otherwise we will continue up to InstrLimit instructions to find
|
||||
// the register which is not defined/used for the longest time.
|
||||
FoundTo = true;
|
||||
Pos = To;
|
||||
}
|
||||
if (FoundTo) {
|
||||
if (Survivor == 0 || !Candidates.test(Survivor)) {
|
||||
int Reg = Candidates.find_first();
|
||||
if (Reg == -1)
|
||||
break;
|
||||
Survivor = Reg;
|
||||
}
|
||||
if (--InstrCountDown == 0 || I == MBB.begin())
|
||||
break;
|
||||
if (FoundVReg) {
|
||||
// Keep searching when we find a vreg since the spilled register will
|
||||
// be usefull for this other vreg as well later.
|
||||
InstrCountDown = InstrLimit;
|
||||
Pos = I;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return std::make_pair(Survivor, Pos);
|
||||
}
|
||||
|
||||
static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
|
||||
unsigned i = 0;
|
||||
while (!MI.getOperand(i).isFI()) {
|
||||
|
@ -427,81 +407,6 @@ static unsigned getFrameIndexOperandNum(MachineInstr &MI) {
|
|||
return i;
|
||||
}
|
||||
|
||||
RegScavenger::ScavengedInfo &
|
||||
RegScavenger::spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
|
||||
MachineBasicBlock::iterator Before,
|
||||
MachineBasicBlock::iterator &UseMI) {
|
||||
// Find an available scavenging slot with size and alignment matching
|
||||
// the requirements of the class RC.
|
||||
const MachineFunction &MF = *Before->getParent()->getParent();
|
||||
const MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
unsigned NeedSize = RC.getSize();
|
||||
unsigned NeedAlign = RC.getAlignment();
|
||||
|
||||
unsigned SI = Scavenged.size(), Diff = UINT_MAX;
|
||||
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
|
||||
for (unsigned I = 0; I < Scavenged.size(); ++I) {
|
||||
if (Scavenged[I].Reg != 0)
|
||||
continue;
|
||||
// Verify that this slot is valid for this register.
|
||||
int FI = Scavenged[I].FrameIndex;
|
||||
if (FI < FIB || FI >= FIE)
|
||||
continue;
|
||||
unsigned S = MFI.getObjectSize(FI);
|
||||
unsigned A = MFI.getObjectAlignment(FI);
|
||||
if (NeedSize > S || NeedAlign > A)
|
||||
continue;
|
||||
// Avoid wasting slots with large size and/or large alignment. Pick one
|
||||
// that is the best fit for this register class (in street metric).
|
||||
// Picking a larger slot than necessary could happen if a slot for a
|
||||
// larger register is reserved before a slot for a smaller one. When
|
||||
// trying to spill a smaller register, the large slot would be found
|
||||
// first, thus making it impossible to spill the larger register later.
|
||||
unsigned D = (S-NeedSize) + (A-NeedAlign);
|
||||
if (D < Diff) {
|
||||
SI = I;
|
||||
Diff = D;
|
||||
}
|
||||
}
|
||||
|
||||
if (SI == Scavenged.size()) {
|
||||
// We need to scavenge a register but have no spill slot, the target
|
||||
// must know how to do it (if not, we'll assert below).
|
||||
Scavenged.push_back(ScavengedInfo(FIE));
|
||||
}
|
||||
|
||||
// Avoid infinite regress
|
||||
Scavenged[SI].Reg = Reg;
|
||||
|
||||
// If the target knows how to save/restore the register, let it do so;
|
||||
// otherwise, use the emergency stack spill slot.
|
||||
if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
|
||||
// Spill the scavenged register before \p Before.
|
||||
int FI = Scavenged[SI].FrameIndex;
|
||||
if (FI < FIB || FI >= FIE) {
|
||||
std::string Msg = std::string("Error while trying to spill ") +
|
||||
TRI->getName(Reg) + " from class " + TRI->getRegClassName(&RC) +
|
||||
": Cannot scavenge register without an emergency spill slot!";
|
||||
report_fatal_error(Msg.c_str());
|
||||
}
|
||||
TII->storeRegToStackSlot(*MBB, Before, Reg, true, Scavenged[SI].FrameIndex,
|
||||
&RC, TRI);
|
||||
MachineBasicBlock::iterator II = std::prev(Before);
|
||||
|
||||
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
|
||||
// Restore the scavenged register before its use (or first terminator).
|
||||
TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
|
||||
&RC, TRI);
|
||||
II = std::prev(UseMI);
|
||||
|
||||
FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
}
|
||||
return Scavenged[SI];
|
||||
}
|
||||
|
||||
unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
|
||||
MachineBasicBlock::iterator I,
|
||||
int SPAdj) {
|
||||
|
@ -534,47 +439,81 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
|
|||
return SReg;
|
||||
}
|
||||
|
||||
ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
|
||||
Scavenged.Restore = &*std::prev(UseMI);
|
||||
// Find an available scavenging slot with size and alignment matching
|
||||
// the requirements of the class RC.
|
||||
const MachineFrameInfo &MFI = MF.getFrameInfo();
|
||||
unsigned NeedSize = RC->getSize();
|
||||
unsigned NeedAlign = RC->getAlignment();
|
||||
|
||||
unsigned SI = Scavenged.size(), Diff = UINT_MAX;
|
||||
int FIB = MFI.getObjectIndexBegin(), FIE = MFI.getObjectIndexEnd();
|
||||
for (unsigned I = 0; I < Scavenged.size(); ++I) {
|
||||
if (Scavenged[I].Reg != 0)
|
||||
continue;
|
||||
// Verify that this slot is valid for this register.
|
||||
int FI = Scavenged[I].FrameIndex;
|
||||
if (FI < FIB || FI >= FIE)
|
||||
continue;
|
||||
unsigned S = MFI.getObjectSize(FI);
|
||||
unsigned A = MFI.getObjectAlignment(FI);
|
||||
if (NeedSize > S || NeedAlign > A)
|
||||
continue;
|
||||
// Avoid wasting slots with large size and/or large alignment. Pick one
|
||||
// that is the best fit for this register class (in street metric).
|
||||
// Picking a larger slot than necessary could happen if a slot for a
|
||||
// larger register is reserved before a slot for a smaller one. When
|
||||
// trying to spill a smaller register, the large slot would be found
|
||||
// first, thus making it impossible to spill the larger register later.
|
||||
unsigned D = (S-NeedSize) + (A-NeedAlign);
|
||||
if (D < Diff) {
|
||||
SI = I;
|
||||
Diff = D;
|
||||
}
|
||||
}
|
||||
|
||||
if (SI == Scavenged.size()) {
|
||||
// We need to scavenge a register but have no spill slot, the target
|
||||
// must know how to do it (if not, we'll assert below).
|
||||
Scavenged.push_back(ScavengedInfo(FIE));
|
||||
}
|
||||
|
||||
// Avoid infinite regress
|
||||
Scavenged[SI].Reg = SReg;
|
||||
|
||||
// If the target knows how to save/restore the register, let it do so;
|
||||
// otherwise, use the emergency stack spill slot.
|
||||
if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SReg)) {
|
||||
// Spill the scavenged register before I.
|
||||
int FI = Scavenged[SI].FrameIndex;
|
||||
if (FI < FIB || FI >= FIE) {
|
||||
std::string Msg = std::string("Error while trying to spill ") +
|
||||
TRI->getName(SReg) + " from class " + TRI->getRegClassName(RC) +
|
||||
": Cannot scavenge register without an emergency spill slot!";
|
||||
report_fatal_error(Msg.c_str());
|
||||
}
|
||||
TII->storeRegToStackSlot(*MBB, I, SReg, true, Scavenged[SI].FrameIndex,
|
||||
RC, TRI);
|
||||
MachineBasicBlock::iterator II = std::prev(I);
|
||||
|
||||
unsigned FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
|
||||
// Restore the scavenged register before its use (or first terminator).
|
||||
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, Scavenged[SI].FrameIndex,
|
||||
RC, TRI);
|
||||
II = std::prev(UseMI);
|
||||
|
||||
FIOperandNum = getFrameIndexOperandNum(*II);
|
||||
TRI->eliminateFrameIndex(II, SPAdj, FIOperandNum, this);
|
||||
}
|
||||
|
||||
Scavenged[SI].Restore = &*std::prev(UseMI);
|
||||
|
||||
// Doing this here leads to infinite regress.
|
||||
// Scavenged[SI].Reg = SReg;
|
||||
|
||||
DEBUG(dbgs() << "Scavenged register (with spill): " << TRI->getName(SReg) <<
|
||||
"\n");
|
||||
|
||||
return SReg;
|
||||
}
|
||||
|
||||
unsigned RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
|
||||
MachineBasicBlock::iterator To,
|
||||
bool RestoreAfter, int SPAdj) {
|
||||
const MachineBasicBlock &MBB = *To->getParent();
|
||||
const MachineFunction &MF = *MBB.getParent();
|
||||
// Consider all allocatable registers in the register class initially
|
||||
BitVector Candidates = TRI->getAllocatableSet(MF, &RC);
|
||||
|
||||
// Try to find a register that's unused if there is one, as then we won't
|
||||
// have to spill.
|
||||
BitVector Available = getRegsAvailable(&RC);
|
||||
|
||||
// Find the register whose use is furthest away.
|
||||
MachineBasicBlock::iterator UseMI;
|
||||
std::pair<unsigned, MachineBasicBlock::iterator> P =
|
||||
findSurvivorBackwards(*TRI, MBBI, To, Available, Candidates);
|
||||
unsigned Reg = P.first;
|
||||
assert(Reg != 0 && "No register left to scavenge!");
|
||||
// Found an available register?
|
||||
if (!Available.test(Reg)) {
|
||||
MachineBasicBlock::iterator ReloadAfter =
|
||||
RestoreAfter ? std::next(MBBI) : MBBI;
|
||||
MachineBasicBlock::iterator ReloadBefore = std::next(ReloadAfter);
|
||||
DEBUG(dbgs() << "Reload before: " << *ReloadBefore << '\n');
|
||||
MachineBasicBlock::iterator SpillBefore = P.second;
|
||||
ScavengedInfo &Scavenged = spill(Reg, RC, SPAdj, SpillBefore, ReloadBefore);
|
||||
Scavenged.Restore = &*std::prev(SpillBefore);
|
||||
LiveUnits.removeReg(Reg);
|
||||
DEBUG(dbgs() << "Scavenged register with spill: " << PrintReg(Reg, TRI)
|
||||
<< " until " << *SpillBefore);
|
||||
} else {
|
||||
DEBUG(dbgs() << "Scavenged free register: " << PrintReg(Reg, TRI) << '\n');
|
||||
}
|
||||
return Reg;
|
||||
}
|
||||
|
|
|
@ -140,8 +140,8 @@ define void @stored_fi_to_global_2_small_objects(float* addrspace(1)* %ptr) #0 {
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset:
|
||||
; GCN-DAG: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc
|
||||
; GCN-DAG: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
|
||||
; GCN: s_add_i32 [[BASE_1_OFF_0:s[0-9]+]], 0, 0x3ffc
|
||||
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
|
||||
; GCN: buffer_store_dword [[BASE_0]], v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
|
||||
|
||||
; GCN: v_mov_b32_e32 [[V_BASE_1_OFF_0:v[0-9]+]], [[BASE_1_OFF_0]]
|
||||
|
|
|
@ -1,62 +1,34 @@
|
|||
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
|
||||
; Check that register scavenging spill slot is close to $fp.
|
||||
target triple="mipsel--"
|
||||
; RUN: llc -march=mipsel -O0 -relocation-model=pic < %s | FileCheck %s
|
||||
|
||||
@var = external global i32
|
||||
@ptrvar = external global i8*
|
||||
; CHECK: sw ${{.*}}, 8($sp)
|
||||
; CHECK: lw ${{.*}}, 8($sp)
|
||||
|
||||
; CHECK-LABEL: func:
|
||||
define void @func() {
|
||||
%space = alloca i32, align 4
|
||||
%stackspace = alloca[16384 x i32], align 4
|
||||
|
||||
; ensure stackspace is not optimized out
|
||||
%stackspace_casted = bitcast [16384 x i32]* %stackspace to i8*
|
||||
store volatile i8* %stackspace_casted, i8** @ptrvar
|
||||
|
||||
; Load values to increase register pressure.
|
||||
%v0 = load volatile i32, i32* @var
|
||||
%v1 = load volatile i32, i32* @var
|
||||
%v2 = load volatile i32, i32* @var
|
||||
%v3 = load volatile i32, i32* @var
|
||||
%v4 = load volatile i32, i32* @var
|
||||
%v5 = load volatile i32, i32* @var
|
||||
%v6 = load volatile i32, i32* @var
|
||||
%v7 = load volatile i32, i32* @var
|
||||
%v8 = load volatile i32, i32* @var
|
||||
%v9 = load volatile i32, i32* @var
|
||||
%v10 = load volatile i32, i32* @var
|
||||
%v11 = load volatile i32, i32* @var
|
||||
%v12 = load volatile i32, i32* @var
|
||||
%v13 = load volatile i32, i32* @var
|
||||
%v14 = load volatile i32, i32* @var
|
||||
%v15 = load volatile i32, i32* @var
|
||||
%v16 = load volatile i32, i32* @var
|
||||
|
||||
; Computing a stack-relative values needs an additional register.
|
||||
; We should get an emergency spill/reload for this.
|
||||
; CHECK: sw ${{.*}}, 0($sp)
|
||||
; CHECK: lw ${{.*}}, 0($sp)
|
||||
store volatile i32 %v0, i32* %space
|
||||
|
||||
; store values so they are used.
|
||||
store volatile i32 %v0, i32* @var
|
||||
store volatile i32 %v1, i32* @var
|
||||
store volatile i32 %v2, i32* @var
|
||||
store volatile i32 %v3, i32* @var
|
||||
store volatile i32 %v4, i32* @var
|
||||
store volatile i32 %v5, i32* @var
|
||||
store volatile i32 %v6, i32* @var
|
||||
store volatile i32 %v7, i32* @var
|
||||
store volatile i32 %v8, i32* @var
|
||||
store volatile i32 %v9, i32* @var
|
||||
store volatile i32 %v10, i32* @var
|
||||
store volatile i32 %v11, i32* @var
|
||||
store volatile i32 %v12, i32* @var
|
||||
store volatile i32 %v13, i32* @var
|
||||
store volatile i32 %v14, i32* @var
|
||||
store volatile i32 %v15, i32* @var
|
||||
store volatile i32 %v16, i32* @var
|
||||
|
||||
ret void
|
||||
define i32 @main(i32 signext %argc, i8** %argv) #0 {
|
||||
entry:
|
||||
%retval = alloca i32, align 4
|
||||
%argc.addr = alloca i32, align 4
|
||||
%argv.addr = alloca i8**, align 4
|
||||
%v0 = alloca <16 x i8>, align 16
|
||||
%.compoundliteral = alloca <16 x i8>, align 16
|
||||
%v1 = alloca <16 x i8>, align 16
|
||||
%.compoundliteral1 = alloca <16 x i8>, align 16
|
||||
%unused_variable = alloca [16384 x i32], align 4
|
||||
%result = alloca <16 x i8>, align 16
|
||||
store i32 0, i32* %retval
|
||||
store i32 %argc, i32* %argc.addr, align 4
|
||||
store i8** %argv, i8*** %argv.addr, align 4
|
||||
store <16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8>* %.compoundliteral
|
||||
%0 = load <16 x i8>, <16 x i8>* %.compoundliteral
|
||||
store <16 x i8> %0, <16 x i8>* %v0, align 16
|
||||
store <16 x i8> zeroinitializer, <16 x i8>* %.compoundliteral1
|
||||
%1 = load <16 x i8>, <16 x i8>* %.compoundliteral1
|
||||
store <16 x i8> %1, <16 x i8>* %v1, align 16
|
||||
%2 = load <16 x i8>, <16 x i8>* %v0, align 16
|
||||
%3 = load <16 x i8>, <16 x i8>* %v1, align 16
|
||||
%mul = mul <16 x i8> %2, %3
|
||||
store <16 x i8> %mul, <16 x i8>* %result, align 16
|
||||
ret i32 0
|
||||
}
|
||||
|
||||
attributes #0 = { noinline "no-frame-pointer-elim"="true" }
|
||||
|
|
|
@ -25,8 +25,8 @@ entry:
|
|||
|
||||
; CHECK-DAG: li [[REG1:[0-9]+]], -128
|
||||
; CHECK-DAG: neg [[REG2:[0-9]+]],
|
||||
; CHECK: and [[REG3:[0-9]+]], [[REG2]], [[REG1]]
|
||||
; CHECK: stdux {{[0-9]+}}, 1, [[REG3]]
|
||||
; CHECK: and [[REG1]], [[REG2]], [[REG1]]
|
||||
; CHECK: stdux {{[0-9]+}}, 1, [[REG1]]
|
||||
|
||||
; CHECK: blr
|
||||
|
||||
|
|
|
@ -46,8 +46,8 @@ define i32 @test3() {
|
|||
; CHECK-LABEL: test3:
|
||||
; CHECK: ldr [[TEMP:r[0-7]]],
|
||||
; CHECK: add sp, [[TEMP]]
|
||||
; CHECK: ldr [[TEMP2:r[0-7]]],
|
||||
; CHECK: add [[TEMP2]], sp
|
||||
; CHECK: ldr [[TEMP]],
|
||||
; CHECK: add [[TEMP]], sp
|
||||
; EABI: ldr [[TEMP:r[0-7]]],
|
||||
; EABI: add sp, [[TEMP]]
|
||||
; IOS: subs r4, r7, #4
|
||||
|
|
Loading…
Reference in New Issue