replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Don't use MRI liveouts in R600. 

Something very strange is going on with the output registers in this
target. Its ISelLowering code is inserting dangling CopyToReg nodes,
hoping that those physregs won't get clobbered before the RETURN.

This patch adds the output registers as implicit uses on RETURN
instructions in the custom emission pass. I'd much prefer to have those
CopyToReg nodes glued to the RETURNs, but I don't see how.

llvm-svn: 174400
This commit is contained in:
Jakob Stoklund Olesen 2013-02-05 17:53:52 +00:00
parent bf034dbd32
commit fdc37670f6
3 changed files with 14 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
llvm/lib/Target/R600/R600ISelLowering.cpp
View File

@ -266,6 +266,15 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
.addImm(EOP);
break;
}
case AMDGPU::RETURN: {
// RETURN instructions must have the live-out registers as implicit uses,
// otherwise they appear dead.
R600MachineFunctionInfo *MFI = MF->getInfo<R600MachineFunctionInfo>();
MachineInstrBuilder MIB(*MF, MI);
for (unsigned i = 0, e = MFI->LiveOuts.size(); i != e; ++i)
MIB.addReg(MFI->LiveOuts[i], RegState::Implicit);
return BB;
}
}
MI->eraseFromParent();
@ -348,12 +357,10 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
switch (IntrinsicID) {
case AMDGPUIntrinsic::AMDGPU_store_output: {
MachineFunction &MF = DAG.getMachineFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex);
if (!MRI.isLiveOut(Reg)) {
MRI.addLiveOut(Reg);
}
MFI->LiveOuts.push_back(Reg);
return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
}
case AMDGPUIntrinsic::R600_store_pixel_color: {

3
llvm/lib/Target/R600/R600Instructions.td
View File

@ -1580,7 +1580,8 @@ def FNEG_R600 : FNEG<R600_Reg32>;
//===---------------------------------------------------------------------===//
// Return instruction
//===---------------------------------------------------------------------===//
let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1,
usesCustomInserter = 1 in {
def RETURN : ILFormat<(outs), (ins variable_ops),
"RETURN", [(IL_retflag)]>;
}

1
llvm/lib/Target/R600/R600MachineFunctionInfo.h
View File

@ -23,6 +23,7 @@ class R600MachineFunctionInfo : public MachineFunctionInfo {
public:
R600MachineFunctionInfo(const MachineFunction &MF);
SmallVector<unsigned, 4> LiveOuts;
SDNode *Outputs[16];
};