replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[AArch64] Add negative tests for the SIMD & FP LDP instructions. 

LDP is unpredictable if the registers in the pair are identical, these tests check that we don't assemble instructions like that and error out instead.

llvm-svn: 213074
This commit is contained in:
Tilmann Scheller 2014-07-15 16:33:24 +00:00
parent 44f3e30cf2
commit fc14cefeea
1 changed files with 36 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
llvm/test/MC/AArch64/arm64-diags.s
View File

@ -159,6 +159,15 @@ ldr q1, [x3, w3, sxtw #1]
ldp w1, w2, [x2], #16 ldp w1, w2, [x2], #16
ldp w2, w2, [x2], #16 ldp w2, w2, [x2], #16
ldp x1, x1, [x2] ldp x1, x1, [x2]
ldp s1, s1, [x1], #8
ldp s1, s1, [x1, #8]!
ldp s1, s1, [x1, #8]
ldp d1, d1, [x1], #16
ldp d1, d1, [x1, #16]!
ldp d1, d1, [x1, #16]
ldp q1, q1, [x1], #32
ldp q1, q1, [x1, #32]!
ldp q1, q1, [x1, #32]
ldr x2, [x2], #8 ldr x2, [x2], #8
ldr x2, [x2, #8]! ldr x2, [x2, #8]!
@ -185,6 +194,33 @@ ldr q1, [x3, w3, sxtw #1]
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp x1, x1, [x2] ; CHECK-ERRORS: ldp x1, x1, [x2]
; CHECK-ERRORS: ^ ; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1], #8
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1, #8]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp s1, s1, [x1, #8]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1], #16
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1, #16]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp d1, d1, [x1, #16]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1], #32
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1, #32]!
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
; CHECK-ERRORS: ldp q1, q1, [x1, #32]
; CHECK-ERRORS: ^
; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
; CHECK-ERRORS: ldr x2, [x2], #8 ; CHECK-ERRORS: ldr x2, [x2], #8
; CHECK-ERRORS: ^ ; CHECK-ERRORS: ^