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[lld][AMDGPU] Handle R_AMDGPU_REL16 relocation. 

This patch is a followup patch to https://reviews.llvm.org/D105760 which adds this relocation. This handles the relocation in lld.

The s_branch family of instruction does the following:
PC = PC + signext(simm * 4) + 4

so we we do the opposite on the target address before writing it in the instruction stream.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105761
This commit is contained in:
Hafiz Abid Qadeer 2021-07-13 19:28:00 +01:00
parent 6296e10972
commit fb9c5c3dce
2 changed files with 45 additions and 0 deletions
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7
lld/ELF/Arch/AMDGPU.cpp
View File

@ -139,6 +139,12 @@ void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
case R_AMDGPU_REL32_HI:
write32le(loc, val >> 32);
break;
case R_AMDGPU_REL16: {
int64_t simm = (static_cast<int64_t>(val) - 4) / 4;
checkInt(loc, simm, 16, rel);
write16le(loc, simm);
break;
}
default:
llvm_unreachable("unknown relocation");
}
@ -154,6 +160,7 @@ RelExpr AMDGPU::getRelExpr(RelType type, const Symbol &s,
case R_AMDGPU_REL32_LO:
case R_AMDGPU_REL32_HI:
case R_AMDGPU_REL64:
case R_AMDGPU_REL16:
return R_PC;
case R_AMDGPU_GOTPCREL:
case R_AMDGPU_GOTPCREL32_LO:

38
lld/test/ELF/amdgpu-relocs2.s Normal file
View File

@ -0,0 +1,38 @@
# REQUIRES: amdgpu
# RUN: split-file %s %t
# RUN: llvm-mc -filetype=obj -triple=amdgcn--amdhsa -mcpu=fiji %t/asm -o %t.o
# RUN: ld.lld %t.o -o %t/out --script %t/script
# RUN: llvm-objdump -d %t/out | FileCheck %s
#--- script
SECTIONS {
. = 0x1000;
.text.likely : { *(.text.likely) }
. = 0x2000;
.text : { *(.text) }
. = 0x3000;
.text.unlikely : { *(.text.unlikely) }
}
#--- asm
.section .text.likely
hot1:
s_add_i32 s15, s15, 1
hot2:
s_add_i32 s13, s13, 1
.text
foo:
s_branch cold2
s_branch hot2
.section .text.unlikely
cold1:
s_add_i32 s15, s15, 1
s_add_i32 s14, s14, 1
cold2:
s_add_i32 s13, s13, 1
# CHECK: <foo>
# CHECK-NEXT: s_branch 1025
# CHECK-NEXT: s_branch 64511