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[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints() 

Finally all targets are enabling multiple regalloc hints, so the hook to
disable this can now be removed.

NFC.

Review: Simon Pilgrim
https://reviews.llvm.org/D52316

llvm-svn: 343851
This commit is contained in:
Jonas Paulsson 2018-10-05 14:23:11 +00:00
parent a78c249af6
commit faad1b3056
13 changed files with 5 additions and 58 deletions
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7
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
View File

@ -824,13 +824,6 @@ public:
// Do nothing.
}
/// The creation of multiple copy hints have been implemented in
/// weightCalcHelper(), but since this affects so many tests for many
/// targets, this is temporarily disabled per default. THIS SHOULD BE
/// "GENERAL GOODNESS" and hopefully all targets will update their tests
/// and enable this soon. This hook should then be removed.
virtual bool enableMultipleCopyHints() const { return false; }
/// Allow the target to reverse allocation order of local live ranges. This
/// will generally allocate shorter local live ranges first. For targets with
/// many registers, this could reduce regalloc compile time by a large

35
llvm/lib/CodeGen/CalcSpillWeights.cpp
View File

@ -70,15 +70,6 @@ static unsigned copyHint(const MachineInstr *mi, unsigned reg,
return sub == hsub ? hreg : 0;
const TargetRegisterClass *rc = mri.getRegClass(reg);
if (!tri.enableMultipleCopyHints()) {
// Only allow physreg hints in rc.
if (sub == 0)
return rc->contains(hreg) ? hreg : 0;
// reg:sub should match the physreg hreg.
return tri.getMatchingSuperReg(hreg, sub, rc);
}
unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
if (rc->contains(CopiedPReg))
return CopiedPReg;
@ -199,31 +190,19 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
unsigned Reg;
float Weight;
bool IsPhys;
unsigned HintOrder;
CopyHint(unsigned R, float W, bool P, unsigned HR) :
Reg(R), Weight(W), IsPhys(P), HintOrder(HR) {}
CopyHint(unsigned R, float W, bool P) :
Reg(R), Weight(W), IsPhys(P) {}
bool operator<(const CopyHint &rhs) const {
// Always prefer any physreg hint.
if (IsPhys != rhs.IsPhys)
return (IsPhys && !rhs.IsPhys);
if (Weight != rhs.Weight)
return (Weight > rhs.Weight);
// This is just a temporary way to achive NFC for targets that don't
// enable multiple copy hints. HintOrder should be removed when all
// targets return true in enableMultipleCopyHints().
return (HintOrder < rhs.HintOrder);
#if 0 // Should replace the HintOrder check, see above.
// (just for the purpose of maintaining the set)
return Reg < rhs.Reg;
#endif
return Reg < rhs.Reg; // Tie-breaker.
}
};
std::set<CopyHint> CopyHints;
// Temporary: see comment for HintOrder above.
unsigned CopyHintOrder = 0;
for (MachineRegisterInfo::reg_instr_iterator
I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
I != E; ) {
@ -263,8 +242,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
}
// Get allocation hints from copies.
if (!mi->isCopy() ||
(TargetHint.first != 0 && !tri.enableMultipleCopyHints()))
if (!mi->isCopy())
continue;
unsigned hint = copyHint(mi, li.reg, tri, mri);
if (!hint)
@ -275,8 +253,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
// FIXME: we probably shouldn't use floats at all.
volatile float hweight = Hint[hint] += weight;
if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint))
CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint),
(tri.enableMultipleCopyHints() ? hint : CopyHintOrder++)));
CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint)));
}
Hint.clear();
@ -294,8 +271,6 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &li, SlotIndex *start,
// Don't add the same reg twice or the target-type hint again.
continue;
mri.addRegAllocationHint(li.reg, Hint.Reg);
if (!tri.enableMultipleCopyHints())
break;
}
// Weakly boost the spill weight of hinted registers.

2
llvm/lib/Target/AArch64/AArch64RegisterInfo.h
View File

@ -84,8 +84,6 @@ public:
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
bool enableMultipleCopyHints() const override { return true; }
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;

2
llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h
View File

@ -27,8 +27,6 @@ class TargetInstrInfo;
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
AMDGPURegisterInfo();
bool enableMultipleCopyHints() const override { return true; }
/// \returns the sub reg enum value for the given \p Channel
/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
static unsigned getSubRegFromChannel(unsigned Channel);

1
llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -156,7 +156,6 @@ public:
void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
bool hasBasePointer(const MachineFunction &MF) const;

2
llvm/lib/Target/BPF/BPFRegisterInfo.h
View File

@ -29,8 +29,6 @@ struct BPFRegisterInfo : public BPFGenRegisterInfo {
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

2
llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
View File

@ -39,8 +39,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;

2
llvm/lib/Target/Mips/MipsRegisterInfo.h
View File

@ -57,8 +57,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;

2
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -85,8 +85,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
/// We require the register scavenger.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;

2
llvm/lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -35,8 +35,6 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const override;
bool enableMultipleCopyHints() const override { return true; }
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

2
llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -57,8 +57,6 @@ public:
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
bool enableMultipleCopyHints() const override { return true; }
// Override TargetRegisterInfo.h.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;

2
llvm/lib/Target/X86/X86RegisterInfo.h
View File

@ -95,8 +95,6 @@ public:
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const MCPhysReg *

2
llvm/lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -33,8 +33,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool enableMultipleCopyHints() const override { return true; }
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;