x86: Emit LAHF/SAHF instead of PUSHF/POPF
NaCl's sandbox doesn't allow PUSHF/POPF out of security concerns (priviledged emulators have forgotten to mask system bits in the past, and EFLAGS's DF bit is a constant source of hilarity). Commit r220529 fixed PR20376 by saving cmpxchg's flags result using EFLAGS, this commit now generated LAHF/SAHF instead, for all of x86 (not just NaCl) because it leads to an overall performance gain over PUSHF/POPF. As with the previous patch this code generation is pretty bad because it occurs very later, after register allocation, and in many cases it rematerializes flags which were already available (e.g. already in a register through SETE). Fortunately it's somewhat rare that this code needs to fire. I did [[ https://github.com/jfbastien/benchmark-x86-flags | a bit of benchmarking ]], the results on an Intel Haswell E5-2690 CPU at 2.9GHz are: | Time per call (ms) | Runtime (ms) | Benchmark | | 0.000012514 | 6257 | sete.i386 | | 0.000012810 | 6405 | sete.i386-fast | | 0.000010456 | 5228 | sete.x86-64 | | 0.000010496 | 5248 | sete.x86-64-fast | | 0.000012906 | 6453 | lahf-sahf.i386 | | 0.000013236 | 6618 | lahf-sahf.i386-fast | | 0.000010580 | 5290 | lahf-sahf.x86-64 | | 0.000010304 | 5152 | lahf-sahf.x86-64-fast | | 0.000028056 | 14028 | pushf-popf.i386 | | 0.000027160 | 13580 | pushf-popf.i386-fast | | 0.000023810 | 11905 | pushf-popf.x86-64 | | 0.000026468 | 13234 | pushf-popf.x86-64-fast | Clearly `PUSHF`/`POPF` are suboptimal. It doesn't really seems to be worth teaching LLVM about individual flags, at least not for this purpose. Reviewers: rnk, jvoung, t.p.northover Subscribers: llvm-commits Differential revision: http://reviews.llvm.org/D6629 llvm-svn: 244503
This commit is contained in:
JF Bastien
parent
00b6f74935
commit
fa9746dc8d
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@ -310,7 +310,7 @@ MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
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if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
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continue;
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bool IsRegOrSuperReg = MOReg == Reg || TRI->isSubRegister(MOReg, Reg);
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bool IsRegOrSuperReg = MOReg == Reg || TRI->isSuperRegister(MOReg, Reg);
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bool IsRegOrOverlapping = MOReg == Reg || TRI->regsOverlap(MOReg, Reg);
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if (IsRegOrSuperReg && MO.readsReg()) {
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@ -3903,35 +3903,60 @@ void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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return;
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}
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// Moving EFLAGS to / from another register requires a push and a pop.
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bool FromEFLAGS = SrcReg == X86::EFLAGS;
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bool ToEFLAGS = DestReg == X86::EFLAGS;
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int Reg = FromEFLAGS ? DestReg : SrcReg;
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bool is32 = X86::GR32RegClass.contains(Reg);
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bool is64 = X86::GR64RegClass.contains(Reg);
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if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
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// The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
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// inefficient. Instead:
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// - Save the overflow flag OF into AL using SETO, and restore it using a
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// signed 8-bit addition of AL and INT8_MAX.
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// - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
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// using LAHF/SAHF.
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// - When RAX/EAX is live and isn't the destination register, make sure it
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// isn't clobbered by PUSH/POP'ing it before and after saving/restoring
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// the flags.
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// This approach is ~2.25x faster than using PUSHF/POPF.
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//
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// This is still somewhat inefficient because we don't know which flags are
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// actually live inside EFLAGS. Were we able to do a single SETcc instead of
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// SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
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//
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// PUSHF/POPF is also potentially incorrect because it affects other flags
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// such as TF/IF/DF, which LLVM doesn't model.
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//
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// Notice that we have to adjust the stack if we don't want to clobber the
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// first frame index. See X86FrameLowering.cpp - clobbersTheStack.
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if (SrcReg == X86::EFLAGS) {
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if (X86::GR64RegClass.contains(DestReg)) {
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BuildMI(MBB, MI, DL, get(X86::PUSHF64));
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BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
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int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
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int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
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int Pop = is64 ? X86::POP64r : X86::POP32r;
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int AX = is64 ? X86::RAX : X86::EAX;
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bool AXDead = (Reg == AX) ||
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(MachineBasicBlock::LQR_Dead ==
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MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
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if (!AXDead)
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BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
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if (FromEFLAGS) {
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BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
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BuildMI(MBB, MI, DL, get(X86::LAHF));
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BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
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}
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if (ToEFLAGS) {
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BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
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BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
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.addReg(X86::AL)
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.addImm(INT8_MAX);
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BuildMI(MBB, MI, DL, get(X86::SAHF));
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}
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if (!AXDead)
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BuildMI(MBB, MI, DL, get(Pop), AX);
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return;
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}
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if (X86::GR32RegClass.contains(DestReg)) {
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BuildMI(MBB, MI, DL, get(X86::PUSHF32));
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BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
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return;
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}
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}
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if (DestReg == X86::EFLAGS) {
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if (X86::GR64RegClass.contains(SrcReg)) {
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BuildMI(MBB, MI, DL, get(X86::PUSH64r))
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.addReg(SrcReg, getKillRegState(KillSrc));
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BuildMI(MBB, MI, DL, get(X86::POPF64));
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return;
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}
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if (X86::GR32RegClass.contains(SrcReg)) {
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BuildMI(MBB, MI, DL, get(X86::PUSH32r))
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.addReg(SrcReg, getKillRegState(KillSrc));
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BuildMI(MBB, MI, DL, get(X86::POPF32));
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return;
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}
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}
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DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
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<< " to " << RI.getName(DestReg) << '\n');
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@ -1,24 +1,58 @@
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; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu %s -o - | FileCheck %s -check-prefix=i386
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; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=i386f
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s -check-prefix=x8664
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=x8664
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declare i32 @bar()
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declare i32 @foo()
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declare i32 @bar(i64)
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define i64 @test_intervening_call(i64* %foo, i64 %bar, i64 %baz) {
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; CHECK-LABEL: test_intervening_call:
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; CHECK: cmpxchg
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; CHECK: pushf[[LQ:[lq]]]
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; CHECK-NEXT: pop[[LQ]] [[FLAGS:%.*]]
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; i386-LABEL: test_intervening_call:
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; i386: cmpxchg8b
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; i386-NEXT: pushl %eax
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; i386-NEXT: seto %al
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; i386-NEXT: lahf
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; i386-NEXT: movl %eax, [[FLAGS:%.*]]
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; i386-NEXT: popl %eax
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; i386-NEXT: movl %edx, 4(%esp)
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; i386-NEXT: movl %eax, (%esp)
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; i386-NEXT: calll bar
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; i386-NEXT: movl [[FLAGS]], %eax
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; i386-NEXT: addb $127, %al
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; i386-NEXT: sahf
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; i386-NEXT: jne
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; CHECK-NEXT: call[[LQ]] bar
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; i386f-LABEL: test_intervening_call:
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; i386f: cmpxchg8b
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; i386f-NEXT: movl %eax, (%esp)
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; i386f-NEXT: movl %edx, 4(%esp)
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; i386f-NEXT: seto %al
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; i386f-NEXT: lahf
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; i386f-NEXT: movl %eax, [[FLAGS:%.*]]
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; i386f-NEXT: calll bar
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; i386f-NEXT: movl [[FLAGS]], %eax
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; i386f-NEXT: addb $127, %al
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; i386f-NEXT: sahf
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; i386f-NEXT: jne
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; x8664-LABEL: test_intervening_call:
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; x8664: cmpxchgq
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; x8664: pushq %rax
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; x8664-NEXT: seto %al
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; x8664-NEXT: lahf
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; x8664-NEXT: movq %rax, [[FLAGS:%.*]]
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; x8664-NEXT: popq %rax
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; x8664-NEXT: movq %rax, %rdi
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; x8664-NEXT: callq bar
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; x8664-NEXT: movq [[FLAGS]], %rax
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; x8664-NEXT: addb $127, %al
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; x8664-NEXT: sahf
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; x8664-NEXT: jne
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; CHECK-NEXT: push[[LQ]] [[FLAGS]]
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; CHECK-NEXT: popf[[LQ]]
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; CHECK-NEXT: jne
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%cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst
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%v = extractvalue { i64, i1 } %cx, 0
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%p = extractvalue { i64, i1 } %cx, 1
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call i32 @bar()
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call i32 @bar(i64 %v)
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br i1 %p, label %t, label %f
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t:
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@ -30,10 +64,18 @@ f:
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; Interesting in producing a clobber without any function calls.
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define i32 @test_control_flow(i32* %p, i32 %i, i32 %j) {
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; CHECK-LABEL: test_control_flow:
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; i386-LABEL: test_control_flow:
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; i386: cmpxchg
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; i386-NEXT: jne
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; i386f-LABEL: test_control_flow:
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; i386f: cmpxchg
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; i386f-NEXT: jne
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; x8664-LABEL: test_control_flow:
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; x8664: cmpxchg
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; x8664-NEXT: jne
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; CHECK: cmpxchg
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; CHECK-NEXT: jne
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entry:
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%cmp = icmp sgt i32 %i, %j
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br i1 %cmp, label %loop_start, label %cond.end
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@ -67,20 +109,46 @@ cond.end:
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; This one is an interesting case because CMOV doesn't have a chain
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; operand. Naive attempts to limit cmpxchg EFLAGS use are likely to fail here.
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define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) {
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; CHECK-LABEL: test_feed_cmov:
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; i386-LABEL: test_feed_cmov:
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; i386: cmpxchgl
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; i386-NEXT: seto %al
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; i386-NEXT: lahf
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; i386-NEXT: movl %eax, [[FLAGS:%.*]]
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; i386-NEXT: calll foo
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; i386-NEXT: pushl %eax
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; i386-NEXT: movl [[FLAGS]], %eax
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; i386-NEXT: addb $127, %al
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; i386-NEXT: sahf
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; i386-NEXT: popl %eax
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; CHECK: cmpxchg
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; CHECK: pushf[[LQ:[lq]]]
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; CHECK-NEXT: pop[[LQ]] [[FLAGS:%.*]]
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; i386f-LABEL: test_feed_cmov:
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; i386f: cmpxchgl
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; i386f-NEXT: seto %al
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; i386f-NEXT: lahf
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; i386f-NEXT: movl %eax, [[FLAGS:%.*]]
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; i386f-NEXT: calll foo
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; i386f-NEXT: pushl %eax
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; i386f-NEXT: movl [[FLAGS]], %eax
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; i386f-NEXT: addb $127, %al
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; i386f-NEXT: sahf
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; i386f-NEXT: popl %eax
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; CHECK-NEXT: call[[LQ]] bar
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; x8664-LABEL: test_feed_cmov:
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; x8664: cmpxchgl
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; x8664: seto %al
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; x8664-NEXT: lahf
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; x8664-NEXT: movq %rax, [[FLAGS:%.*]]
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; x8664-NEXT: callq foo
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; x8664-NEXT: pushq %rax
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; x8664-NEXT: movq [[FLAGS]], %rax
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; x8664-NEXT: addb $127, %al
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; x8664-NEXT: sahf
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; x8664-NEXT: popq %rax
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; CHECK-NEXT: push[[LQ]] [[FLAGS]]
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; CHECK-NEXT: popf[[LQ]]
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%res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst seq_cst
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%success = extractvalue { i32, i1 } %res, 1
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%rhs = call i32 @bar()
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%rhs = call i32 @foo()
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%ret = select i1 %success, i32 %new, i32 %rhs
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ret i32 %ret
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