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Add correct encodings for the basic variants for vst2. 

llvm-svn: 118068
This commit is contained in:
Owen Anderson 2010-11-02 21:16:58 +00:00
parent 87c62e54e6
commit fa08e1e277
2 changed files with 52 additions and 30 deletions
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70
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -921,21 +921,27 @@ def VST1d64QPseudo_UPD : VSTQQWBPseudo<IIC_VST1x4u>;
// VST2 : Vector Store (multiple 2-element structures)
class VST2D<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2),
IIC_VST2, "vst2", Dt, "\\{$src1, $src2\\}, $addr", "", []>;
(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2),
IIC_VST2, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn", "", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
}
class VST2Q<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0011, op7_4, (outs),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST2x2, "vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr",
"", []>;
(ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
IIC_VST2x2, "vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
"", []> {
let Rm = 0b1111;
let Inst{5-4} = Rn{5-4};
}
def VST2d8 : VST2D<0b1000, 0b0000, "8">;
def VST2d16 : VST2D<0b1000, 0b0100, "16">;
def VST2d32 : VST2D<0b1000, 0b1000, "32">;
def VST2d8 : VST2D<0b1000, {0,0,?,?}, "8">;
def VST2d16 : VST2D<0b1000, {0,1,?,?}, "16">;
def VST2d32 : VST2D<0b1000, {1,0,?,?}, "32">;
def VST2q8 : VST2Q<0b0000, "8">;
def VST2q16 : VST2Q<0b0100, "16">;
def VST2q32 : VST2Q<0b1000, "32">;
def VST2q8 : VST2Q<{0,0,?,?}, "8">;
def VST2q16 : VST2Q<{0,1,?,?}, "16">;
def VST2q32 : VST2Q<{1,0,?,?}, "32">;
def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
@ -948,23 +954,27 @@ def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
// ...with address register writeback:
class VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset, DPR:$src1, DPR:$src2),
IIC_VST2u, "vst2", Dt, "\\{$src1, $src2\\}, $addr$offset",
"$addr.addr = $wb", []>;
(ins addrmode6:$Rn, am6offset:$Rm, DPR:$Vd, DPR:$src2),
IIC_VST2u, "vst2", Dt, "\\{$Vd, $src2\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
}
class VST2QWB<bits<4> op7_4, string Dt>
: NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
(ins addrmode6:$addr, am6offset:$offset,
DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
"vst2", Dt, "\\{$src1, $src2, $src3, $src4\\}, $addr$offset",
"$addr.addr = $wb", []>;
(ins addrmode6:$Rn, am6offset:$Rm,
DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST2x2u,
"vst2", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
}
def VST2d8_UPD : VST2DWB<0b1000, 0b0000, "8">;
def VST2d16_UPD : VST2DWB<0b1000, 0b0100, "16">;
def VST2d32_UPD : VST2DWB<0b1000, 0b1000, "32">;
def VST2d8_UPD : VST2DWB<0b1000, {0,0,?,?}, "8">;
def VST2d16_UPD : VST2DWB<0b1000, {0,1,?,?}, "16">;
def VST2d32_UPD : VST2DWB<0b1000, {1,0,?,?}, "32">;
def VST2q8_UPD : VST2QWB<0b0000, "8">;
def VST2q16_UPD : VST2QWB<0b0100, "16">;
def VST2q32_UPD : VST2QWB<0b1000, "32">;
def VST2q8_UPD : VST2QWB<{0,0,?,?}, "8">;
def VST2q16_UPD : VST2QWB<{0,1,?,?}, "16">;
def VST2q32_UPD : VST2QWB<{1,0,?,?}, "32">;
def VST2d8Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
def VST2d16Pseudo_UPD : VSTQWBPseudo<IIC_VST2u>;
@ -975,12 +985,12 @@ def VST2q16Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
def VST2q32Pseudo_UPD : VSTQQWBPseudo<IIC_VST2x2u>;
// ...with double-spaced registers (for disassembly only):
def VST2b8 : VST2D<0b1001, 0b0000, "8">;
def VST2b16 : VST2D<0b1001, 0b0100, "16">;
def VST2b32 : VST2D<0b1001, 0b1000, "32">;
def VST2b8_UPD : VST2DWB<0b1001, 0b0000, "8">;
def VST2b16_UPD : VST2DWB<0b1001, 0b0100, "16">;
def VST2b32_UPD : VST2DWB<0b1001, 0b1000, "32">;
def VST2b8 : VST2D<0b1001, {0,0,?,?}, "8">;
def VST2b16 : VST2D<0b1001, {0,1,?,?}, "16">;
def VST2b32 : VST2D<0b1001, {1,0,?,?}, "32">;
def VST2b8_UPD : VST2DWB<0b1001, {0,0,?,?}, "8">;
def VST2b16_UPD : VST2DWB<0b1001, {0,1,?,?}, "16">;
def VST2b32_UPD : VST2DWB<0b1001, {1,0,?,?}, "32">;
// VST3 : Vector Store (multiple 3-element structures)
class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>

12
llvm/test/MC/ARM/neon-vst-encoding.s
View File

@ -18,3 +18,15 @@
@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4]
vst1.64 {d16, d17}, [r0]
@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
vst2.8 {d16, d17}, [r0, :64]
@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
vst2.16 {d16, d17}, [r0, :128]
@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4]
vst2.32 {d16, d17}, [r0]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4]
vst2.8 {d16, d17, d18, d19}, [r0, :64]
@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4]
vst2.16 {d16, d17, d18, d19}, [r0, :128]
@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4]
vst2.32 {d16, d17, d18, d19}, [r0, :256]