From f99637cb4da3568d40110fc1dbd9dbc0d9789f91 Mon Sep 17 00:00:00 2001
From: Daniel Sanders <daniel.sanders@imgtec.com>
Date: Mon, 12 May 2014 15:43:41 +0000
Subject: [PATCH] Revert: r208582 - [mips][mips64r6] Add sel.s and sel.d

Accidentally committed an unreviewed patch. Reverted it.

llvm-svn: 208583
---
 llvm/lib/Target/Mips/Mips32r6InstrFormats.td | 39 +-------------------
 llvm/lib/Target/Mips/Mips32r6InstrInfo.td    | 17 +--------
 llvm/test/MC/Mips/mips32r6/valid.s           |  2 -
 llvm/test/MC/Mips/mips64r6/valid.s           |  2 -
 4 files changed, 4 insertions(+), 56 deletions(-)

diff --git a/llvm/lib/Target/Mips/Mips32r6InstrFormats.td b/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
index 4471870fa316..241cde2a8256 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrFormats.td
@@ -17,42 +17,6 @@ class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
   let EncodingPredicates = [HasStdEnc];
 }
 
-//===----------------------------------------------------------------------===//
-//
-// Field Values
-//
-//===----------------------------------------------------------------------===//
-
-def OPGROUP_COP1 { bits<6> Value = 0b010001; }
-def OPGROUP_SPECIAL { bits<6> Value = 0b000000; }
-
-class FIELD_FMT<bits<5> Val> {
-  bits<5> Value = Val;
-}
-def FIELD_FMT_S : FIELD_FMT<0b10000>;
-def FIELD_FMT_D : FIELD_FMT<0b10001>;
-
-//===----------------------------------------------------------------------===//
-//
-// Encoding Formats
-//
-//===----------------------------------------------------------------------===//
-
-class COP1_SEL_FM<FIELD_FMT Format> : MipsR6Inst {
-  bits<5> ft;
-  bits<5> fs;
-  bits<5> fd;
-
-  bits<32> Inst;
-
-  let Inst{31-26} = OPGROUP_COP1.Value;
-  let Inst{25-21} = Format.Value;
-  let Inst{20-16} = ft;
-  let Inst{15-11} = fs;
-  let Inst{10-6} = fd;
-  let Inst{5-0} = 0b010000;
-}
-
 class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
   bits<5> rd;
   bits<5> rs;
@@ -60,10 +24,11 @@ class SPECIAL_3R_FM<bits<5> mulop, bits<6> funct> : MipsR6Inst {
 
   bits<32> Inst;
 
-  let Inst{31-26} = OPGROUP_SPECIAL.Value;
+  let Inst{31-26} = 0b00000;
   let Inst{25-21} = rs;
   let Inst{20-16} = rt;
   let Inst{15-11} = rd;
   let Inst{10-6}  = mulop;
   let Inst{5-0}   = funct;
 }
+
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 16cd29919413..95a22d0052c1 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -68,8 +68,6 @@ class MUH_ENC    : SPECIAL_3R_FM<0b00011, 0b011000>;
 class MUHU_ENC   : SPECIAL_3R_FM<0b00011, 0b011001>;
 class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>;
 class MULU_ENC   : SPECIAL_3R_FM<0b00010, 0b011001>;
-class SEL_D_ENC  : COP1_SEL_FM<FIELD_FMT_D>;
-class SEL_S_ENC  : COP1_SEL_FM<FIELD_FMT_S>;
 
 //===----------------------------------------------------------------------===//
 //
@@ -101,17 +99,6 @@ class MUHU_DESC   : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>;
 class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>;
 class MULU_DESC   : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>;
 
-class SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> {
-  dag OutOperandList = (outs FGROpnd:$fd);
-  dag InOperandList = (ins FGROpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft);
-  string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft");
-  list<dag> Pattern = [];
-  string Constraints = "$fd_in = $fd";
-}
-
-class SEL_D_DESC : SEL_DESC_BASE<"sel.d", FGR64Opnd>;
-class SEL_S_DESC : SEL_DESC_BASE<"sel.s", FGR32Opnd>;
-
 //===----------------------------------------------------------------------===//
 //
 // Instruction Definitions
@@ -185,5 +172,5 @@ def SELEQZ_S;
 def SELNEZ;
 def SELNEZ_D;
 def SELNEZ_S;
-def SEL_D : SEL_D_ENC, SEL_D_DESC, ISA_MIPS32R6;
-def SEL_S : SEL_S_ENC, SEL_S_DESC, ISA_MIPS32R6;
+def SEL_D;
+def SEL_S;
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index 0fd6741b8b6a..c822a15466e1 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -12,5 +12,3 @@
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
         mulu    $2,$3,$4         # CHECK: mulu $2, $3, $4  # encoding: [0x00,0x64,0x10,0x99]
         muhu    $2,$3,$4         # CHECK: muhu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xd9]
-        sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
-        sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]
diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s
index 29b6704f870f..fcac87a1fd7e 100644
--- a/llvm/test/MC/Mips/mips64r6/valid.s
+++ b/llvm/test/MC/Mips/mips64r6/valid.s
@@ -20,5 +20,3 @@
         dmuh    $2,$3,$4         # CHECK: dmuh $2, $3, $4  # encoding: [0x00,0x64,0x10,0xf8]
         dmulu   $2,$3,$4         # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9]
         dmuhu   $2,$3,$4         # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9]
-        sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
-        sel.s   $f0,$f1,$f2      # CHECK: sel.s $f0, $f1, $f2 # encoding: [0x46,0x02,0x08,0x10]