Remove the "Register ®" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC()
methods of EmulateInstructionARM class. The context data structure should provide sufficient information already. llvm-svn: 125596
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@ -176,7 +176,7 @@ public:
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eInfoTypeAddress,
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eInfoTypeModeAndImmediate,
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eInfoTypeModeAndImmediateSigned,
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eInfoTypeModeAndRegister,
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eInfoTypeMode,
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eInfoTypeNoArgs
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} InfoType;
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@ -241,11 +241,7 @@ public:
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int32_t signed_data_value; // signed immdiate data
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} ModeAndImmediateSigned;
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struct ModeAndRegister
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{
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uint32_t mode; // eModeARM or eModeThumb
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Register reg;
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} ModeAndRegister;
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} info;
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@ -329,11 +325,10 @@ public:
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}
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void
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SetModeAndRegister (uint32_t mode, Register reg)
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SetMode (uint32_t mode)
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{
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info_type = eInfoTypeModeAndRegister;
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info.ModeAndRegister.mode = mode;
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info.ModeAndRegister.reg = reg;
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info_type = eInfoTypeMode;
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info.mode = mode;
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}
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void
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@ -427,7 +427,7 @@ EmulateInstructionARM::EmulatePop (ARMEncoding encoding)
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if (!success)
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return false;
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, dwarf_reg))
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if (!LoadWritePC(context, data))
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return false;
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addr += addr_byte_size;
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}
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@ -628,7 +628,7 @@ EmulateInstructionARM::EmulateMovRdRm (ARMEncoding encoding)
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if (Rd == 15)
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{
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if (!ALUWritePC (context, reg_value, dwarf_reg))
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if (!ALUWritePC (context, reg_value))
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return false;
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}
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else
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@ -711,12 +711,9 @@ EmulateInstructionARM::EmulateMovRdImm (ARMEncoding encoding)
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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Register dummy_reg;
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dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
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if (Rd == 15)
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{
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if (!ALUWritePC (context, result, dummy_reg))
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if (!ALUWritePC (context, result))
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return false;
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}
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else
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@ -801,8 +798,7 @@ EmulateInstructionARM::EmulateMvnRdImm (ARMEncoding encoding)
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if (Rd == 15)
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{
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Register dummy_reg;
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if (!ALUWritePC (context, result, dummy_reg))
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if (!ALUWritePC (context, result))
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return false;
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}
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else
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@ -909,7 +905,7 @@ EmulateInstructionARM::EmulateLDRRtPCRelative (ARMEncoding encoding)
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if (Bits32(address, 1, 0) == 0)
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{
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, pc_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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else
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@ -1205,7 +1201,7 @@ EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding)
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context.SetRegister (dwarf_reg);
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if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
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return false;
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if (!BXWritePC(context, target, dwarf_reg))
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if (!BXWritePC(context, target))
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return false;
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}
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return true;
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@ -1253,7 +1249,8 @@ EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding)
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Register dwarf_reg;
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dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
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if (!BXWritePC(context, target, dwarf_reg))
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context.SetRegister (dwarf_reg);
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if (!BXWritePC(context, target))
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return false;
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}
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return true;
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@ -1964,12 +1961,10 @@ EmulateInstructionARM::EmulateAddRdnRm (ARMEncoding encoding)
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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Register dummy_reg;
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dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
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if (Rd == 15)
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{
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if (!ALUWritePC (context, result, dummy_reg))
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if (!ALUWritePC (context, result))
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return false;
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}
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else
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@ -2181,12 +2176,9 @@ EmulateInstructionARM::EmulateASRImm (ARMEncoding encoding)
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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Register dummy_reg;
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dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
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if (Rd == 15)
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{
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if (!ALUWritePC (context, result, dummy_reg))
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if (!ALUWritePC (context, result))
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return false;
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}
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else
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@ -2333,7 +2325,7 @@ EmulateInstructionARM::EmulateLDM (ARMEncoding encoding)
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if (!success)
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return false;
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, dwarf_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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@ -2449,7 +2441,7 @@ EmulateInstructionARM::EmulateLDMDA (ARMEncoding encoding)
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if (!success)
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return false;
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, dwarf_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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@ -2590,7 +2582,7 @@ EmulateInstructionARM::EmulateLDMDB (ARMEncoding encoding)
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if (!success)
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return false;
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, dwarf_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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@ -2707,7 +2699,7 @@ EmulateInstructionARM::EmulateLDMIB (ARMEncoding encoding)
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if (!success)
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return false;
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// In ARMv5T and above, this is an interworking branch.
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if (!LoadWritePC(context, data, dwarf_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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@ -2809,8 +2801,6 @@ EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding)
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EmulateInstruction::Context context;
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context.type = EmulateInstruction::eContextImmediate;
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context.SetNoArgs ();
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Register dummy_reg;
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dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
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// Read memory from the address.
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data = ReadMemoryUnsigned(context, address, 4, 0, &success);
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@ -2821,7 +2811,7 @@ EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding)
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{
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if (Bits32(address, 1, 0) == 0)
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{
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if (!LoadWritePC(context, data, dummy_reg))
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if (!LoadWritePC(context, data))
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return false;
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}
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else
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@ -3831,7 +3821,7 @@ EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr)
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// As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr.
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bool
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EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register ®)
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EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr)
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{
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addr_t target;
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// If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
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@ -3847,7 +3837,7 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register ®
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cpsr_changed = true;
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}
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target = addr & 0xfffffffe;
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context.SetModeAndRegister (eModeThumb, reg);
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context.SetMode (eModeThumb);
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}
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else if (BitIsClear(addr, 1))
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{
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@ -3857,7 +3847,7 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register ®
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cpsr_changed = true;
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}
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target = addr & 0xfffffffc;
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context.SetModeAndRegister (eModeARM, reg);
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context.SetMode (eModeARM);
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}
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else
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return false; // address<1:0> == '10' => UNPREDICTABLE
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@ -3875,20 +3865,20 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register ®
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// Dispatches to either BXWritePC or BranchWritePC based on architecture versions.
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bool
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EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr, Register ®)
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EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr)
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{
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if (ArchVersion() >= ARMv5T)
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return BXWritePC(context, addr, reg);
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return BXWritePC(context, addr);
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else
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return BranchWritePC((const Context)context, addr);
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}
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// Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set.
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bool
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EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr, Register ®)
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EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr)
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{
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if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM)
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return BXWritePC(context, addr, reg);
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return BXWritePC(context, addr);
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else
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return BranchWritePC((const Context)context, addr);
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}
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@ -158,13 +158,13 @@ public:
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BranchWritePC(const Context &context, uint32_t addr);
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bool
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BXWritePC(Context &context, uint32_t addr, Register ®);
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BXWritePC(Context &context, uint32_t addr);
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bool
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LoadWritePC(Context &context, uint32_t addr, Register ®);
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LoadWritePC(Context &context, uint32_t addr);
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bool
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ALUWritePC(Context &context, uint32_t addr, Register ®);
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ALUWritePC(Context &context, uint32_t addr);
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Mode
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CurrentInstrSet();
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