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Change MRC and MRC2 instructions to model the output register properly 

llvm-svn: 128085
This commit is contained in:
Bruno Cardoso Lopes 2011-03-22 15:06:24 +00:00
parent 7413080cea
commit f922b20922
3 changed files with 37 additions and 24 deletions
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33
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -3489,10 +3489,9 @@ defm STC2 : LdStCop<0b1111, 0, "stc2">;
// Move between coprocessor and ARM core register -- for disassembly only
//
class MovRCopro<string opc, bit direction>
: ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
NoItinerary, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
class MovRCopro<string opc, bit direction, dag oops, dag iops>
: ABI<0b1110, oops, iops, NoItinerary, opc,
"\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> {
let Inst{20} = direction;
let Inst{4} = 1;
@ -3512,13 +3511,17 @@ class MovRCopro<string opc, bit direction>
let Inst{19-16} = CRn;
}
def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
i32imm:$opc2)>;
def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
class MovRCopro2<string opc, bit direction>
: ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
class MovRCopro2<string opc, bit direction, dag oops, dag iops>
: ABXI<0b1110, oops, iops, NoItinerary,
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111;
let Inst{20} = direction;
@ -3539,8 +3542,14 @@ class MovRCopro2<string opc, bit direction>
let Inst{19-16} = CRn;
}
def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */>;
def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */>;
def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
i32imm:$opc2)>;
def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRn, c_imm:$CRm,
i32imm:$opc2)>;
class MovRRCopro<string opc, bit direction>
: ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,

14
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -1322,10 +1322,8 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
// Move between coprocessor and ARM core register -- for disassembly only
//
class tMovRCopro<string opc, bit direction>
: T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
class tMovRCopro<string opc, bit direction, dag oops, dag iops>
: T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1110;
let Inst{20} = direction;
@ -1346,8 +1344,12 @@ class tMovRCopro<string opc, bit direction>
let Inst{19-16} = CRn;
}
def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>;
def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>;
class tMovRRCopro<string opc, bit direction>
: T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),

14
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3330,10 +3330,8 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
// Move between coprocessor and ARM core register -- for disassembly only
//
class t2MovRCopro<string opc, bit direction>
: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
class t2MovRCopro<string opc, bit direction, dag oops, dag iops>
: T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1110;
let Inst{20} = direction;
@ -3354,8 +3352,12 @@ class t2MovRCopro<string opc, bit direction>
let Inst{19-16} = CRn;
}
def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */>;
def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */>;
def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>;
def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>;
class t2MovRRCopro<string opc, bit direction>
: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),