Recognize unpckh* masks and match 256-bit versions. The new versions are
different from the previous 128-bit because they work in lanes. Update a few comments and add testcases llvm-svn: 136157
This commit is contained in:
Bruno Cardoso Lopes
parent
9eb62cd159
commit
f8fe47bd2b
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@ -167,23 +167,22 @@ void DecodeUNPCKLPMask(EVT VT,
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SmallVectorImpl<unsigned> &ShuffleMask) {
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unsigned NumElts = VT.getVectorNumElements();
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElts / NumSections;
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits() / 128;
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if (NumLanes == 0 ) NumLanes = 1; // Handle MMX
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unsigned NumLaneElts = NumElts / NumLanes;
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unsigned Start = 0;
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unsigned End = NumSectionElts / 2;
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for (unsigned s = 0; s < NumSections; ++s) {
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unsigned End = NumLaneElts / 2;
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for (unsigned s = 0; s < NumLanes; ++s) {
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for (unsigned i = Start; i != End; ++i) {
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ShuffleMask.push_back(i); // Reads from dest/src1
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ShuffleMask.push_back(i+NumSectionElts); // Reads from src/src2
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ShuffleMask.push_back(i+NumLaneElts); // Reads from src/src2
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}
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// Process the next 128 bits.
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Start += NumSectionElts;
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End += NumSectionElts;
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Start += NumLaneElts;
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End += NumLaneElts;
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}
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}
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@ -2711,6 +2711,8 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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@ -2782,6 +2784,8 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::PUNPCKLQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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@ -3219,20 +3223,22 @@ bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) {
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static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool V2IsSplat = false) {
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int NumElts = VT.getVectorNumElements();
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if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
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assert((VT.is128BitVector() || VT.is256BitVector()) &&
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"Unsupported vector type for unpckh");
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if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
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return false;
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElts / NumSections;
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits()/128;
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unsigned NumLaneElts = NumElts/NumLanes;
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unsigned Start = 0;
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unsigned End = NumSectionElts;
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for (unsigned s = 0; s < NumSections; ++s) {
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for (unsigned i = Start, j = s * NumSectionElts;
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unsigned End = NumLaneElts;
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for (unsigned s = 0; s < NumLanes; ++s) {
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for (unsigned i = Start, j = s * NumLaneElts;
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i != End;
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i += 2, ++j) {
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int BitI = Mask[i];
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@ -3248,8 +3254,8 @@ static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT,
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}
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}
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// Process the next 128 bits.
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Start += NumSectionElts;
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End += NumSectionElts;
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Start += NumLaneElts;
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End += NumLaneElts;
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}
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return true;
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@ -3266,21 +3272,38 @@ bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) {
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static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool V2IsSplat = false) {
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int NumElts = VT.getVectorNumElements();
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if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16)
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assert((VT.is128BitVector() || VT.is256BitVector()) &&
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"Unsupported vector type for unpckh");
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if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8)
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return false;
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for (int i = 0, j = 0; i != NumElts; i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j + NumElts/2))
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return false;
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if (V2IsSplat) {
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if (isUndefOrEqual(BitI1, NumElts))
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return false;
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} else {
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if (!isUndefOrEqual(BitI1, j + NumElts/2 + NumElts))
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits()/128;
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unsigned NumLaneElts = NumElts/NumLanes;
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unsigned Start = 0;
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unsigned End = NumLaneElts;
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for (unsigned l = 0; l != NumLanes; ++l) {
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for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2;
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i != End; i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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if (!isUndefOrEqual(BitI, j))
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return false;
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if (V2IsSplat) {
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if (isUndefOrEqual(BitI1, NumElts))
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return false;
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} else {
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if (!isUndefOrEqual(BitI1, j+NumElts))
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return false;
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}
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}
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// Process the next 128 bits.
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Start += NumLaneElts;
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End += NumLaneElts;
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}
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return true;
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}
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@ -3299,16 +3322,14 @@ static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) {
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if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16)
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return false;
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// Handle vector lengths > 128 bits. Define a "section" as a set of
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// 128 bits. AVX defines UNPCK* to operate independently on 128-bit
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// sections.
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unsigned NumSections = VT.getSizeInBits() / 128;
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if (NumSections == 0 ) NumSections = 1; // Handle MMX
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unsigned NumSectionElts = NumElems / NumSections;
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// Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate
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// independently on 128-bit lanes.
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unsigned NumLanes = VT.getSizeInBits() / 128;
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unsigned NumLaneElts = NumElems / NumLanes;
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for (unsigned s = 0; s < NumSections; ++s) {
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for (unsigned i = s * NumSectionElts, j = s * NumSectionElts;
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i != NumSectionElts * (s + 1);
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for (unsigned s = 0; s < NumLanes; ++s) {
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for (unsigned i = s * NumLaneElts, j = s * NumLaneElts;
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i != NumLaneElts * (s + 1);
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i += 2, ++j) {
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int BitI = Mask[i];
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int BitI1 = Mask[i+1];
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@ -4095,6 +4116,8 @@ static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG,
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break;
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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DecodeUNPCKHPMask(NumElems, ShuffleMask);
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break;
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case X86ISD::PUNPCKLBW:
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@ -5751,6 +5774,8 @@ static inline unsigned getUNPCKHOpcode(EVT VT) {
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case MVT::v2i64: return X86ISD::PUNPCKHQDQ;
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case MVT::v4f32: return X86ISD::UNPCKHPS;
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case MVT::v2f64: return X86ISD::UNPCKHPD;
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case MVT::v8f32: return X86ISD::VUNPCKHPSY;
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case MVT::v4f64: return X86ISD::VUNPCKHPDY;
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case MVT::v16i8: return X86ISD::PUNPCKHBW;
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case MVT::v8i16: return X86ISD::PUNPCKHWD;
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default:
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@ -12597,6 +12622,8 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::PUNPCKHQDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::UNPCKHPD:
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case X86ISD::VUNPCKHPSY:
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case X86ISD::VUNPCKHPDY:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLDQ:
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@ -261,6 +261,8 @@ namespace llvm {
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VUNPCKLPDY,
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UNPCKHPS,
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UNPCKHPD,
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VUNPCKHPSY,
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VUNPCKHPDY,
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PUNPCKLBW,
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PUNPCKLWD,
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PUNPCKLDQ,
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@ -133,12 +133,15 @@ def X86Movhlpd : SDNode<"X86ISD::MOVHLPD", SDTShuff2Op>;
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def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
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def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
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def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
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def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
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def X86Unpcklps : SDNode<"X86ISD::UNPCKLPS", SDTShuff2Op>;
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def X86Unpcklpd : SDNode<"X86ISD::UNPCKLPD", SDTShuff2Op>;
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def X86Unpcklpsy : SDNode<"X86ISD::VUNPCKLPSY", SDTShuff2Op>;
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def X86Unpcklpdy : SDNode<"X86ISD::VUNPCKLPDY", SDTShuff2Op>;
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def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
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def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
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def X86Unpckhps : SDNode<"X86ISD::UNPCKHPS", SDTShuff2Op>;
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def X86Unpckhpd : SDNode<"X86ISD::UNPCKHPD", SDTShuff2Op>;
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def X86Unpckhpsy : SDNode<"X86ISD::VUNPCKHPSY", SDTShuff2Op>;
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def X86Unpckhpdy : SDNode<"X86ISD::VUNPCKHPDY", SDTShuff2Op>;
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def X86Punpcklbw : SDNode<"X86ISD::PUNPCKLBW", SDTShuff2Op>;
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def X86Punpcklwd : SDNode<"X86ISD::PUNPCKLWD", SDTShuff2Op>;
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@ -5677,6 +5677,12 @@ def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
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(UNPCKHPSrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKHPSY
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v8f32 (X86Unpckhpsy VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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// Shuffle with UNPCKLPD
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def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
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@ -5703,6 +5709,12 @@ def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
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(UNPCKHPDrr VR128:$src1, VR128:$src2)>;
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// Shuffle with VUNPCKHPDY
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
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def : Pat<(v4f64 (X86Unpckhpdy VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
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// Shuffle with MOVLHPS
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def : Pat<(X86Movlhps VR128:$src1,
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(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
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@ -1,5 +0,0 @@
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load_lib llvm.exp
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if { [llvm_supports_target X86] } {
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RunLLVMTests [lsort [glob -nocomplain $srcdir/$subdir/*.{ll,c,cpp}]]
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}
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@ -1,20 +0,0 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) {
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entry:
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%incarray1 = alloca [2 x <4 x double>]*, align 8
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%incarrayb1 = alloca [2 x <4 x double>]*, align 8
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%carray = alloca [2 x <4 x double>], align 16
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%r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0
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%r3 = load <4 x double>* %r, align 8
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%r4 = load <4 x double>* %rb, align 8
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%r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x double>> [#uses=1]
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; CHECK-NOT: vunpcklpd %ymm
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%r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1
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store <4 x double> %r11, <4 x double>* %r12, align 4
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ret void
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}
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@ -1,20 +0,0 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) {
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enmtry:
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%incarray1 = alloca [2 x <8 x float>]*, align 8
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%incarrayb1 = alloca [2 x <8 x float>]*, align 8
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%carray = alloca [2 x <8 x float>], align 16
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%r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0
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%r3 = load <8 x float>* %r, align 8
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%r4 = load <8 x float>* %rb, align 8
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%r8 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x float>> [#uses=1]
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; CHECK-NOT: vunpcklps %ymm
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%r9 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 0
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store <8 x float> %r8, <8 x float>* %r9, align 4
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ret void
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}
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@ -1,20 +0,0 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
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target triple = "x86_64-unknown-linux-gnu"
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define void @try_([2 x <4 x double>]* noalias %incarray, [2 x <4 x double>]* noalias %incarrayb ) {
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entry:
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%incarray1 = alloca [2 x <4 x double>]*, align 8
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%incarrayb1 = alloca [2 x <4 x double>]*, align 8
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%carray = alloca [2 x <4 x double>], align 16
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%r = getelementptr [2 x <4 x double>]* %incarray, i32 0, i32 0
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%rb = getelementptr [2 x <4 x double>]* %incarrayb, i32 0, i32 0
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%r3 = load <4 x double>* %r, align 8
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%r4 = load <4 x double>* %rb, align 8
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%r11 = shufflevector <4 x double> %r3, <4 x double> %r4, <4 x i32> < i32 0, i32 4, i32 2, i32 6 > ; <<4 x double>> [#uses=1]
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; CHECK: vunpcklpd
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%r12 = getelementptr [2 x <4 x double>]* %carray, i32 0, i32 1
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store <4 x double> %r11, <4 x double>* %r12, align 4
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ret void
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}
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@ -1,20 +0,0 @@
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; RUN: llc < %s -mattr=+avx | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
|
||||
target triple = "x86_64-unknown-linux-gnu"
|
||||
|
||||
define void @try_([2 x <8 x float>]* noalias %incarray, [2 x <8 x float>]* noalias %incarrayb ) {
|
||||
entry:
|
||||
%incarray1 = alloca [2 x <8 x float>]*, align 8
|
||||
%incarrayb1 = alloca [2 x <8 x float>]*, align 8
|
||||
%carray = alloca [2 x <8 x float>], align 16
|
||||
%r = getelementptr [2 x <8 x float>]* %incarray, i32 0, i32 0
|
||||
%rb = getelementptr [2 x <8 x float>]* %incarrayb, i32 0, i32 0
|
||||
%r3 = load <8 x float>* %r, align 8
|
||||
%r4 = load <8 x float>* %rb, align 8
|
||||
%r11 = shufflevector <8 x float> %r3, <8 x float> %r4, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13 > ; <<8 x float>> [#uses=1]
|
||||
; CHECK: vunpcklps
|
||||
%r12 = getelementptr [2 x <8 x float>]* %carray, i32 0, i32 1
|
||||
store <8 x float> %r11, <8 x float>* %r12, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
|
||||
|
||||
; CHECK: vunpckhps
|
||||
define <8 x float> @unpackhips(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 6, i32 14, i32 7, i32 15>
|
||||
ret <8 x float> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK: vunpckhpd
|
||||
define <4 x double> @unpackhipd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
|
||||
ret <4 x double> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK: vunpcklps
|
||||
define <8 x float> @unpacklops(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 4, i32 12, i32 5, i32 13>
|
||||
ret <8 x float> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK: vunpcklpd
|
||||
define <4 x double> @unpacklopd(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
|
||||
ret <4 x double> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK-NOT: vunpcklps %ymm
|
||||
define <8 x float> @unpacklops-not(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
|
||||
ret <8 x float> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK-NOT: vunpcklpd %ymm
|
||||
define <4 x double> @unpacklopd-not(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||||
ret <4 x double> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK-NOT: vunpckhps %ymm
|
||||
define <8 x float> @unpackhips-not(<8 x float> %src1, <8 x float> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <8 x float> %src1, <8 x float> %src2, <8 x i32> <i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13>
|
||||
ret <8 x float> %shuffle.i
|
||||
}
|
||||
|
||||
; CHECK-NOT: vunpckhpd %ymm
|
||||
define <4 x double> @unpackhipd-not(<4 x double> %src1, <4 x double> %src2) nounwind uwtable readnone ssp {
|
||||
entry:
|
||||
%shuffle.i = shufflevector <4 x double> %src1, <4 x double> %src2, <4 x i32> <i32 2, i32 6, i32 3, i32 7>
|
||||
ret <4 x double> %shuffle.i
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue