[PowerPC] Eliminate compares - add i64 sext/zext handling for SETLE/SETGE
As mentioned in https://reviews.llvm.org/D33718, this simply adds another pattern to the compare elimination sequence and is committed without a differential review. llvm-svn: 314073
This commit is contained in:
Nemanja Ivanovic
parent
eb5c411218
commit
f894ce35d0
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@ -3216,6 +3216,8 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
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ISD::CondCode CC,
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int64_t RHSValue, SDLoc dl) {
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bool IsRHSZero = RHSValue == 0;
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bool IsRHSOne = RHSValue == 1;
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bool IsRHSNegOne = RHSValue == -1LL;
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switch (CC) {
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default: return SDValue();
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case ISD::SETEQ: {
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@ -3242,6 +3244,51 @@ SDValue PPCDAGToDAGISel::get64BitZExtCompare(SDValue LHS, SDValue RHS,
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return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, AC,
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Xor, AC.getValue(1)), 0);
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}
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case ISD::SETGE: {
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// {subc.reg, subc.CA} = (subcarry %a, %b)
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// (zext (setcc %a, %b, setge)) ->
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// (adde (lshr %b, 63), (ashr %a, 63), subc.CA)
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// (zext (setcc %a, 0, setge)) -> (lshr (~ %a), 63)
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if (IsRHSZero)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLE: {
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// {subc.reg, subc.CA} = (subcarry %b, %a)
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// (zext (setcc %a, %b, setge)) ->
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// (adde (lshr %a, 63), (ashr %b, 63), subc.CA)
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// (zext (setcc %a, 0, setge)) -> (lshr (or %a, (add %a, -1)), 63)
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if (IsRHSZero)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
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SDValue ShiftL =
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SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
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getI64Imm(1, dl), getI64Imm(63, dl)), 0);
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SDValue ShiftR =
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SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
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getI64Imm(63, dl)), 0);
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SDValue SubtractCarry =
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SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
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LHS, RHS), 1);
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return SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
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ShiftR, ShiftL, SubtractCarry), 0);
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}
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case ISD::SETGT: {
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if (IsRHSNegOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLT: {
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if (IsRHSOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
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return SDValue();
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}
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}
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}
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@ -3251,6 +3298,8 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
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ISD::CondCode CC,
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int64_t RHSValue, SDLoc dl) {
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bool IsRHSZero = RHSValue == 0;
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bool IsRHSOne = RHSValue == 1;
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bool IsRHSNegOne = RHSValue == -1LL;
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switch (CC) {
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default: return SDValue();
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case ISD::SETEQ: {
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@ -3279,6 +3328,53 @@ SDValue PPCDAGToDAGISel::get64BitSExtCompare(SDValue LHS, SDValue RHS,
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return SDValue(CurDAG->getMachineNode(PPC::SUBFE8, dl, MVT::i64, SC,
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SC, SC.getValue(1)), 0);
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}
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case ISD::SETGE: {
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// {subc.reg, subc.CA} = (subcarry %a, %b)
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// (zext (setcc %a, %b, setge)) ->
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// (- (adde (lshr %b, 63), (ashr %a, 63), subc.CA))
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// (zext (setcc %a, 0, setge)) -> (~ (ashr %a, 63))
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if (IsRHSZero)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLE: {
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// {subc.reg, subc.CA} = (subcarry %b, %a)
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// (zext (setcc %a, %b, setge)) ->
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// (- (adde (lshr %a, 63), (ashr %b, 63), subc.CA))
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// (zext (setcc %a, 0, setge)) -> (ashr (or %a, (add %a, -1)), 63)
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if (IsRHSZero)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
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SDValue ShiftR =
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SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, RHS,
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getI64Imm(63, dl)), 0);
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SDValue ShiftL =
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SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, LHS,
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getI64Imm(1, dl), getI64Imm(63, dl)), 0);
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SDValue SubtractCarry =
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SDValue(CurDAG->getMachineNode(PPC::SUBFC8, dl, MVT::i64, MVT::Glue,
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LHS, RHS), 1);
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SDValue Adde =
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SDValue(CurDAG->getMachineNode(PPC::ADDE8, dl, MVT::i64, MVT::Glue,
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ShiftR, ShiftL, SubtractCarry), 0);
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return SDValue(CurDAG->getMachineNode(PPC::NEG8, dl, MVT::i64, Adde), 0);
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}
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case ISD::SETGT: {
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if (IsRHSNegOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
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std::swap(LHS, RHS);
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ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
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IsRHSZero = RHSConst && RHSConst->isNullValue();
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IsRHSOne = RHSConst && RHSConst->getSExtValue() == 1;
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LLVM_FALLTHROUGH;
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}
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case ISD::SETLT: {
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if (IsRHSOne)
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return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
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return SDValue();
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}
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}
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}
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@ -0,0 +1,128 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i64 0, align 8
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define signext i32 @test_igesll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r5, r3, 63
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; CHECK-NEXT: rldicl r6, r4, 1, 63
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r5, r3, 63
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; CHECK-NEXT: rldicl r6, r4, 1, 63
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_igesll_z(i64 %a) {
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; CHECK-LABEL: test_igesll_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_igesll_sext_z(i64 %a) {
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; CHECK-LABEL: test_igesll_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: not r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_igesll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi r6, r3, 63
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; CHECK: subfc r3, r4, r3
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; CHECK: rldicl r3, r4, 1, 63
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; CHECK: adde r3, r6, r3
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; CHECK: std r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_igesll_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r6, r3, 63
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; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
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; CHECK-NEXT: subfc r3, r4, r3
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; CHECK-NEXT: rldicl r3, r4, 1, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
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; CHECK-NEXT: adde r3, r6, r3
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sge i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_z_store(i64 %a) {
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; CHECK-LABEL: test_igesll_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: xori r3, r3, 1
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_igesll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_igesll_sext_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: not r3, r3
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; CHECK-NEXT: std r3,
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sgt i64 %a, -1
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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@ -0,0 +1,130 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
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; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
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; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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@glob = common local_unnamed_addr global i64 0, align 8
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define signext i32 @test_ilesll(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subfc r12, r3, r4
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_sext:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: sradi r5, r4, 63
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; CHECK-NEXT: rldicl r6, r3, 1, 63
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; CHECK-NEXT: subfc r12, r3, r4
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; CHECK-NEXT: adde r3, r5, r6
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; CHECK-NEXT: neg r3, r3
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define signext i32 @test_ilesll_z(i64 %a) {
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; CHECK-LABEL: test_ilesll_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: or r3, r4, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define signext i32 @test_ilesll_sext_z(i64 %a) {
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; CHECK-LABEL: test_ilesll_sext_z:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addi r4, r3, -1
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; CHECK-NEXT: or r3, r4, r3
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; CHECK-NEXT: sradi r3, r3, 63
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%sub = sext i1 %cmp to i32
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ret i32 %sub
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}
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define void @test_ilesll_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi r6, r4, 63
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; CHECK: subfc r4, r3, r4
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; CHECK: rldicl r3, r3, 1, 63
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; CHECK: adde r3, r6, r3
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; CHECK: std r3,
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_sext_store(i64 %a, i64 %b) {
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; CHECK-LABEL: test_ilesll_sext_store:
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; CHECK: # BB#0: # %entry
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; CHECK: sradi r6, r4, 63
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; CHECK-DAG: rldicl r3, r3, 1, 63
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; CHECK-DAG: subfc r4, r3, r4
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; CHECK: adde r3, r6, r3
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; CHECK: neg r3, r3
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; CHECK: std r3,
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp sle i64 %a, %b
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%conv1 = sext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_z_store(i64 %a) {
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; CHECK-LABEL: test_ilesll_z_store:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: addi r5, r3, -1
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: or r3, r5, r3
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; CHECK-NEXT: rldicl r3, r3, 1, 63
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; CHECK-NEXT: std r3, 0(r4)
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; CHECK-NEXT: blr
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entry:
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%cmp = icmp slt i64 %a, 1
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%conv1 = zext i1 %cmp to i64
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store i64 %conv1, i64* @glob, align 8
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ret void
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}
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define void @test_ilesll_sext_z_store(i64 %a) {
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; CHECK-LABEL: test_ilesll_sext_z_store:
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; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addi r5, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: or r3, r5, r3
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 1
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
define i64 @test_llgesll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgesll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r3, 63
|
||||
; CHECK-NEXT: rldicl r6, r4, 1, 63
|
||||
; CHECK-NEXT: subfc r3, r4, r3
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
define i64 @test_llgesll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgesll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r3, 63
|
||||
; CHECK-NEXT: rldicl r6, r4, 1, 63
|
||||
; CHECK-NEXT: subfc r3, r4, r3
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
define i64 @test_llgesll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llgesll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, -1
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
define i64 @test_llgesll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_llgesll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: not r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, -1
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
define void @test_llgesll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgesll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi r6, r3, 63
|
||||
; CHECK: subfc r3, r4, r3
|
||||
; CHECK: rldicl r3, r4, 1, 63
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: std r3,
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_llgesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_llgesll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r6, r3, 63
|
||||
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: subfc r3, r4, r3
|
||||
; CHECK-NEXT: rldicl r3, r4, 1, 63
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
|
||||
; CHECK-NEXT: adde r3, r6, r3
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sge i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_llgesll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llgesll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: xori r3, r3, 1
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, -1
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_llgesll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_llgesll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: not r3, r3
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sgt i64 %a, -1
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||||
; RUN: -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
|
||||
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
@glob = common local_unnamed_addr global i64 0, align 8
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lllesll(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lllesll_sext(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll_sext:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: sradi r5, r4, 63
|
||||
; CHECK-NEXT: rldicl r6, r3, 1, 63
|
||||
; CHECK-NEXT: subfc r12, r3, r4
|
||||
; CHECK-NEXT: adde r3, r5, r6
|
||||
; CHECK-NEXT: neg r3, r3
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lllesll_z(i64 %a) {
|
||||
; CHECK-LABEL: test_lllesll_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addi r4, r3, -1
|
||||
; CHECK-NEXT: or r3, r4, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 1
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind readnone
|
||||
define i64 @test_lllesll_sext_z(i64 %a) {
|
||||
; CHECK-LABEL: test_lllesll_sext_z:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addi r4, r3, -1
|
||||
; CHECK-NEXT: or r3, r4, r3
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 1
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
ret i64 %conv1
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lllesll_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK: subfc r4, r3, r4
|
||||
; CHECK: rldicl r3, r3, 1, 63
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: std r3,
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lllesll_sext_store(i64 %a, i64 %b) {
|
||||
; CHECK-LABEL: test_lllesll_sext_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK: sradi r6, r4, 63
|
||||
; CHECK-DAG: rldicl r3, r3, 1, 63
|
||||
; CHECK-DAG: subfc r4, r3, r4
|
||||
; CHECK: adde r3, r6, r3
|
||||
; CHECK: neg r3, r3
|
||||
; CHECK: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp sle i64 %a, %b
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lllesll_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_lllesll_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addi r5, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: or r3, r5, r3
|
||||
; CHECK-NEXT: rldicl r3, r3, 1, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 1
|
||||
%conv1 = zext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; Function Attrs: norecurse nounwind
|
||||
define void @test_lllesll_sext_z_store(i64 %a) {
|
||||
; CHECK-LABEL: test_lllesll_sext_z_store:
|
||||
; CHECK: # BB#0: # %entry
|
||||
; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
|
||||
; CHECK-NEXT: addi r5, r3, -1
|
||||
; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
|
||||
; CHECK-NEXT: or r3, r5, r3
|
||||
; CHECK-NEXT: sradi r3, r3, 63
|
||||
; CHECK-NEXT: std r3, 0(r4)
|
||||
; CHECK-NEXT: blr
|
||||
entry:
|
||||
%cmp = icmp slt i64 %a, 1
|
||||
%conv1 = sext i1 %cmp to i64
|
||||
store i64 %conv1, i64* @glob, align 8
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue