Fix weak symbols on arm and aarch64.
Given .weak target .global _start _start: b target The intention is that the branch goes to the instruction after the branch, effectively turning it on a nop. The branch adds the runtime PC, but we were adding it statically too. I noticed the oddity by inspection, but llvm-objdump seems to agree, since it now prints things like: b #-4 <_start+0x4> llvm-svn: 305212
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@ -403,7 +403,7 @@ static uint32_t getARMUndefinedRelativeWeakVA(uint32_t Type, uint32_t A,
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uint32_t P) {
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switch (Type) {
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case R_ARM_THM_JUMP11:
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return P + 2;
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return P + 2 + A;
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case R_ARM_CALL:
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case R_ARM_JUMP24:
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case R_ARM_PC24:
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@ -411,12 +411,12 @@ static uint32_t getARMUndefinedRelativeWeakVA(uint32_t Type, uint32_t A,
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case R_ARM_PREL31:
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case R_ARM_THM_JUMP19:
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case R_ARM_THM_JUMP24:
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return P + 4;
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return P + 4 + A;
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case R_ARM_THM_CALL:
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// We don't want an interworking BLX to ARM
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return P + 5;
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return P + 5 + A;
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default:
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return A;
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return P + A;
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}
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}
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@ -427,9 +427,9 @@ static uint64_t getAArch64UndefinedRelativeWeakVA(uint64_t Type, uint64_t A,
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case R_AARCH64_CONDBR19:
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case R_AARCH64_JUMP26:
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case R_AARCH64_TSTBR14:
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return P + 4;
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return P + 4 + A;
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default:
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return A;
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return P + A;
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}
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}
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@ -515,20 +515,30 @@ static uint64_t getRelocTargetVA(uint32_t Type, int64_t A, uint64_t P,
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return InX::MipsGot->getVA() + InX::MipsGot->getTlsOffset() +
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InX::MipsGot->getTlsIndexOff() - InX::MipsGot->getGp();
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case R_PAGE_PC:
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case R_PLT_PAGE_PC:
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case R_PLT_PAGE_PC: {
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uint64_t Dest;
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if (Body.isUndefined() && !Body.isLocal() && Body.symbol()->isWeak())
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return getAArch64Page(A);
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return getAArch64Page(Body.getVA(A)) - getAArch64Page(P);
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case R_PC:
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Dest = getAArch64Page(A);
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else
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Dest = getAArch64Page(Body.getVA(A));
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return Dest - getAArch64Page(P);
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}
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case R_PC: {
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uint64_t Dest;
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if (Body.isUndefined() && !Body.isLocal() && Body.symbol()->isWeak()) {
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// On ARM and AArch64 a branch to an undefined weak resolves to the
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// next instruction, otherwise the place.
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if (Config->EMachine == EM_ARM)
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return getARMUndefinedRelativeWeakVA(Type, A, P);
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if (Config->EMachine == EM_AARCH64)
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return getAArch64UndefinedRelativeWeakVA(Type, A, P);
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Dest = getARMUndefinedRelativeWeakVA(Type, A, P);
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else if (Config->EMachine == EM_AARCH64)
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Dest = getAArch64UndefinedRelativeWeakVA(Type, A, P);
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else
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Dest = Body.getVA(A);
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} else {
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Dest = Body.getVA(A);
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}
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return Dest - P;
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}
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return Body.getVA(A) - P;
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case R_PLT:
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return Body.getPltVA() + A;
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case R_PLT_PC:
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@ -33,12 +33,12 @@ _start:
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// CHECK: Disassembly of section .text:
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// 131076 = 0x20004
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// CHECK: 20000: {{.*}} b #131076
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// CHECK-NEXT: 20004: {{.*}} bl #131080
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// CHECK-NEXT: 20008: {{.*}} b.eq #131084
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// CHECK-NEXT: 2000c: {{.*}} cbz x1, #131088
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// CHECK: 20000: {{.*}} b #4
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// CHECK-NEXT: 20004: {{.*}} bl #4
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// CHECK-NEXT: 20008: {{.*}} b.eq #4
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// CHECK-NEXT: 2000c: {{.*}} cbz x1, #4
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// CHECK-NEXT: 20010: {{.*}} adr x0, #0
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// CHECK-NEXT: 20014: {{.*}} adrp x0, #0
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// CHECK-NEXT: 20014: {{.*}} adrp x0, #-131072
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// CHECK: 20018: {{.*}} .word 0x00000000
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// CHECK-NEXT: 2001c: {{.*}} .word 0x00000000
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// CHECK-NEXT: 20020: {{.*}} .word 0x00000000
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@ -19,6 +19,6 @@ _start:
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// CHECK: Disassembly of section .text:
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// CHECK-NEXT: _start:
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// 69636 = 0x11004 = next instruction
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// CHECK: 11000: {{.*}} bl #69636
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// CHECK-NEXT: 11004: {{.*}} b.w #69640
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// CHECK-NEXT: 11008: {{.*}} b.w #69644
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// CHECK: 11000: {{.*}} bl #0
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// CHECK-NEXT: 11004: {{.*}} b.w #0 <_start+0x8>
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// CHECK-NEXT: 11008: {{.*}} b.w #0 <_start+0xC>
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@ -29,10 +29,10 @@ _start:
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// CHECK: Disassembly of section .text:
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// 69636 = 0x11004
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// CHECK: 11000: {{.*}} beq.w #69636
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// CHECK-NEXT: 11004: {{.*}} b.w #69640
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// CHECK-NEXT: 11008: {{.*}} bl #69644
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// CHECK: 11000: {{.*}} beq.w #0 <_start+0x4>
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// CHECK-NEXT: 11004: {{.*}} b.w #0 <_start+0x8>
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// CHECK-NEXT: 11008: {{.*}} bl #0
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// blx is transformed into bl so we don't change state
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// CHECK-NEXT: 1100c: {{.*}} bl #69648
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// CHECK-NEXT: 1100c: {{.*}} bl #0
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// CHECK-NEXT: 11010: {{.*}} movt r0, #0
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// CHECK-NEXT: 11014: {{.*}} movw r0, #0
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@ -29,10 +29,10 @@ _start:
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// CHECK: Disassembly of section .text:
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// 69636 = 0x11004
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// CHECK: 11000: {{.*}} b #69636
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// CHECK-NEXT: 11004: {{.*}} bl #69640
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// CHECK: 11000: {{.*}} b #-4 <_start+0x4>
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// CHECK-NEXT: 11004: {{.*}} bl #-4 <_start+0x8>
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// blx is transformed into bl so we don't change state
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// CHECK-NEXT: 11008: {{.*}} bl #69644
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// CHECK-NEXT: 11008: {{.*}} bl #-4 <_start+0xC>
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// CHECK-NEXT: 1100c: {{.*}} movt r0, #0
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// CHECK-NEXT: 11010: {{.*}} movw r0, #0
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// CHECK: 11014: {{.*}} .word 0x00000000
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