From f833fad81381e36391560b983885ed29cc8995c0 Mon Sep 17 00:00:00 2001 From: Johnny Chen Date: Sat, 20 Mar 2010 00:17:00 +0000 Subject: [PATCH] Add NLdStFrm Format. llvm-svn: 99014 --- llvm/lib/Target/ARM/ARMInstrFormats.td | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrFormats.td b/llvm/lib/Target/ARM/ARMInstrFormats.td index 5af654ae047d..4f6f05d40943 100644 --- a/llvm/lib/Target/ARM/ARMInstrFormats.td +++ b/llvm/lib/Target/ARM/ARMInstrFormats.td @@ -59,6 +59,8 @@ def NEONDupFrm : Format<28>; def MiscFrm : Format<29>; def ThumbMiscFrm : Format<30>; +def NLdStFrm : Format<31>; + // Misc flags. // the instruction has a Rn register operand. @@ -1464,9 +1466,10 @@ class AVConv5I opcod1, bits<4> opcod2, dag oops, dag iops, // ARM NEON Instruction templates. // -class NeonI pattern> - : InstARM { +class NeonI pattern> + : InstARM { let OutOperandList = oops; let InOperandList = !con(iops, (ins pred:$p)); let AsmString = !strconcat( @@ -1502,8 +1505,8 @@ class NI4 op21_20, bits<4> op11_8, bits<4> op7_4, dag oops, dag iops, InstrItinClass itin, string opc, string dt, string asm, string cstr, list pattern> - : NeonI { + : NeonI { let Inst{31-24} = 0b11110100; let Inst{23} = op23; let Inst{21-20} = op21_20; @@ -1513,7 +1516,7 @@ class NLdSt op21_20, bits<4> op11_8, bits<4> op7_4, class NDataI pattern> - : NeonI { let Inst{31-25} = 0b1111001; }