replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

rename these nodes 

llvm-svn: 26848
This commit is contained in:
Chris Lattner 2006-03-19 01:13:28 +00:00
parent f4e1a53647
commit f7b6e7212f
2 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -179,10 +179,10 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ADD , MVT::v4i32, Legal);
setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
// FIXME: We don't support any ConstantVec's yet. We should custom expand
// FIXME: We don't support any BUILD_VECTOR's yet. We should custom expand
// the ones we do!
setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
}
setSetCCResultContents(ZeroOrOneSetCCResult);

18
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -263,9 +263,9 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
// FIXME: add MMX packed arithmetics
setOperationAction(ISD::ConstantVec, MVT::v8i8, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
}
if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
@ -275,7 +275,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SUB , MVT::v4f32, Legal);
setOperationAction(ISD::MUL , MVT::v4f32, Legal);
setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
}
if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
@ -290,11 +290,11 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::SUB , MVT::v2f64, Legal);
setOperationAction(ISD::MUL , MVT::v2f64, Legal);
setOperationAction(ISD::LOAD , MVT::v2f64, Legal);
setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
}
computeRegisterProperties();