Implement LowerOperationWrapper for legalizer.
Also a few signed comparison fixes. llvm-svn: 62665
This commit is contained in:
parent
ed7d79fce4
commit
f737337707
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@ -31,7 +31,11 @@ namespace PIC16CC {
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LT,
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LE,
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GT,
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GE
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GE,
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ULT,
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UGT,
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ULE,
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UGE
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};
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}
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@ -41,12 +45,32 @@ namespace PIC16CC {
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case PIC16CC::NE: return "ne";
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case PIC16CC::EQ: return "eq";
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case PIC16CC::LT: return "lt";
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case PIC16CC::ULT: return "lt";
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case PIC16CC::LE: return "le";
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case PIC16CC::GT: return "gt";
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case PIC16CC::UGT: return "gt";
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case PIC16CC::GE: return "ge";
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}
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}
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inline static bool isSignedComparison(PIC16CC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case PIC16CC::NE:
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case PIC16CC::EQ:
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case PIC16CC::LT:
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case PIC16CC::LE:
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case PIC16CC::GE:
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case PIC16CC::GT:
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return true;
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case PIC16CC::ULT:
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case PIC16CC::UGT:
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case PIC16CC::ULE:
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case PIC16CC::UGE:
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return false; // condition codes for unsigned comparison.
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}
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}
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FunctionPass *createPIC16ISelDag(PIC16TargetMachine &TM);
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FunctionPass *createPIC16CodePrinterPass(raw_ostream &OS,
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@ -41,21 +41,27 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
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setShiftAmountFlavor(Extend);
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// SRA library call names
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setPIC16LibCallName(PIC16ISD::SRA_I8, "__intrinsics.sra.i8");
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setPIC16LibCallName(PIC16ISD::SRA_I16, "__intrinsics.sra.i16");
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setPIC16LibCallName(PIC16ISD::SRA_I32, "__intrinsics.sra.i32");
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setPIC16LibcallName(PIC16ISD::SRA_I8, "__intrinsics.sra.i8");
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setLibcallName(RTLIB::SRA_I16, "__intrinsics.sra.i16");
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setLibcallName(RTLIB::SRA_I32, "__intrinsics.sra.i32");
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// SLL library call names
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setPIC16LibCallName(PIC16ISD::SLL_I8, "__intrinsics.sll.i8");
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setPIC16LibCallName(PIC16ISD::SLL_I16, "__intrinsics.sll.i16");
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setPIC16LibCallName(PIC16ISD::SLL_I32, "__intrinsics.sll.i32");
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// SHL library call names
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setPIC16LibcallName(PIC16ISD::SLL_I8, "__intrinsics.sll.i8");
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setLibcallName(RTLIB::SHL_I16, "__intrinsics.sll.i16");
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setLibcallName(RTLIB::SHL_I32, "__intrinsics.sll.i32");
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// SRL library call names
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setPIC16LibCallName(PIC16ISD::SRL_I8, "__intrinsics.srl.i8");
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setPIC16LibCallName(PIC16ISD::SRL_I16, "__intrinsics.srl.i16");
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setPIC16LibCallName(PIC16ISD::SRL_I32, "__intrinsics.srl.i32");
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setPIC16LibcallName(PIC16ISD::SRL_I8, "__intrinsics.srl.i8");
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setLibcallName(RTLIB::SRL_I16, "__intrinsics.srl.i16");
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setLibcallName(RTLIB::SRL_I32, "__intrinsics.srl.i32");
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// MUL Library call names
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setPIC16LibcallName(PIC16ISD::MUL_I8, "__intrinsics.mul.i8");
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setLibcallName(RTLIB::MUL_I16, "__intrinsics.mul.i16");
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setLibcallName(RTLIB::MUL_I32, "__intrinsics.mul.i32");
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom);
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setOperationAction(ISD::LOAD, MVT::i8, Legal);
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setOperationAction(ISD::LOAD, MVT::i16, Custom);
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@ -69,7 +75,7 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
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setOperationAction(ISD::ADDC, MVT::i8, Custom);
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setOperationAction(ISD::SUBE, MVT::i8, Custom);
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setOperationAction(ISD::SUBC, MVT::i8, Custom);
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setOperationAction(ISD::ADD, MVT::i8, Legal);
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setOperationAction(ISD::ADD, MVT::i8, Custom);
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setOperationAction(ISD::ADD, MVT::i16, Custom);
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setOperationAction(ISD::OR, MVT::i8, Custom);
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@ -80,16 +86,44 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM)
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setOperationAction(ISD::CALL, MVT::i16, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::SRA, MVT::i8, Custom);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::SRA, MVT::i32, Custom);
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setOperationAction(ISD::MUL, MVT::i8, Custom);
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setOperationAction(ISD::MUL, MVT::i16, Expand);
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setOperationAction(ISD::MUL, MVT::i32, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand);
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setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand);
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setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
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setOperationAction(ISD::MULHU, MVT::i8, Expand);
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setOperationAction(ISD::MULHU, MVT::i16, Expand);
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setOperationAction(ISD::MULHU, MVT::i32, Expand);
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setOperationAction(ISD::MULHS, MVT::i8, Expand);
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setOperationAction(ISD::MULHS, MVT::i16, Expand);
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setOperationAction(ISD::MULHS, MVT::i32, Expand);
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setOperationAction(ISD::SRA, MVT::i8, Custom);
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setOperationAction(ISD::SRA, MVT::i16, Expand);
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setOperationAction(ISD::SRA, MVT::i32, Expand);
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setOperationAction(ISD::SHL, MVT::i8, Custom);
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setOperationAction(ISD::SHL, MVT::i16, Expand);
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setOperationAction(ISD::SHL, MVT::i32, Expand);
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setOperationAction(ISD::SRL, MVT::i8, Custom);
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setOperationAction(ISD::SRL, MVT::i16, Expand);
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setOperationAction(ISD::SRL, MVT::i32, Expand);
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// PIC16 does not support shift parts
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setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SHL, MVT::i8, Custom);
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setOperationAction(ISD::SHL, MVT::i16, Custom);
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setOperationAction(ISD::SHL, MVT::i32, Custom);
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setOperationAction(ISD::SRL, MVT::i8, Custom);
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setOperationAction(ISD::SRL, MVT::i16, Custom);
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setOperationAction(ISD::SRL, MVT::i32, Custom);
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// PIC16 does not have a SETCC, expand it to SELECT_CC.
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setOperationAction(ISD::SETCC, MVT::i8, Expand);
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@ -124,18 +158,18 @@ MVT PIC16TargetLowering::getSetCCResultType(MVT ValType) const {
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void
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PIC16TargetLowering::setPIC16LibCallName(PIC16ISD::PIC16LibCall Call,
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PIC16TargetLowering::setPIC16LibcallName(PIC16ISD::PIC16Libcall Call,
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const char *Name) {
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PIC16LibCallNames[Call] = Name;
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PIC16LibcallNames[Call] = Name;
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}
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const char *
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PIC16TargetLowering::getPIC16LibCallName(PIC16ISD::PIC16LibCall Call) {
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return PIC16LibCallNames[Call];
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PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) {
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return PIC16LibcallNames[Call];
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}
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SDValue
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PIC16TargetLowering::MakePIC16LibCall(PIC16ISD::PIC16LibCall Call,
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PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
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MVT RetVT, const SDValue *Ops,
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unsigned NumOps, bool isSigned,
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SelectionDAG &DAG) {
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@ -151,7 +185,7 @@ PIC16TargetLowering::MakePIC16LibCall(PIC16ISD::PIC16LibCall Call,
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Entry.isZExt = !isSigned;
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Args.push_back(Entry);
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}
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SDValue Callee = DAG.getExternalSymbol(getPIC16LibCallName(Call), MVT::i8);
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SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
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const Type *RetTy = RetVT.getTypeForMVT();
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std::pair<SDValue,SDValue> CallInfo =
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@ -247,15 +281,6 @@ void PIC16TargetLowering::ReplaceNodeResults(SDNode *N,
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case ISD::ADD:
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// Results.push_back(ExpandAdd(N, DAG));
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return;
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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{
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SDValue Res = ExpandShift(N, DAG);
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if (Res.getNode())
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Results.push_back(Res);
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return;
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}
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case ISD::FrameIndex:
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Results.push_back(ExpandFrameIndex(N, DAG));
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return;
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@ -708,94 +733,64 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) {
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return DAG.getNode(ISD::MERGE_VALUES, Tys, BP, Chain);
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}
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SDValue PIC16TargetLowering::ExpandShift(SDNode *N, SelectionDAG &DAG) {
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SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) {
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// We should have handled larger operands in type legalizer itself.
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assert (Op.getValueType() == MVT::i8 && "illegal shift to lower");
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SDNode *N = Op.getNode();
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SDValue Value = N->getOperand(0);
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SDValue Amt = N->getOperand(1);
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SDValue BCF, BCFInput;
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SDValue ShfCom; // Shift Component - Lo component should be shifted
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SDValue RotCom; // Rotate Component- Hi component should be rotated
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PIC16ISD::PIC16LibCall CallCode;
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// Shift amount should be MVT::i8 only. If it is more than that then
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// extract MVT::i8 from that
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if (Amt.getValueType() == MVT::i8) {
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// Do Nothing - This is ok
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} else if (Amt.getValueType() == MVT::i16) {
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SDValue Lo, Hi;
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GetExpandedParts(Amt, DAG, Lo, Hi);
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Amt = Lo; // Take the Lo part as amount
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} else if (Amt.getValueType() == MVT::i32) {
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SDValue Lo, Hi;
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// Get MVT::i16 Components
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GetExpandedParts(Amt, DAG, Lo, Hi);
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// Get MVT::i8 Components
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GetExpandedParts(Lo, DAG, Lo, Hi);
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Amt = Lo;
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} else {
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assert ( 0 && "Invalid Shift amount");
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}
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// Shift library call will always have two operands
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if (N->getValueType(0) == MVT::i8) {
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switch (N->getOpcode()) {
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case ISD::SRA:
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CallCode = PIC16ISD::SRA_I8;
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break;
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case ISD::SHL:
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CallCode = PIC16ISD::SLL_I8;
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break;
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case ISD::SRL:
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CallCode = PIC16ISD::SRL_I8;
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break;
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default:
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assert ( 0 && "This shift is not implemented yet.");
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return SDValue();
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}
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} else if (N->getValueType(0) == MVT::i16) {
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switch (N->getOpcode()) {
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case ISD::SRA:
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CallCode = PIC16ISD::SRA_I16;
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break;
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case ISD::SHL:
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CallCode = PIC16ISD::SLL_I16;
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break;
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case ISD::SRL:
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CallCode = PIC16ISD::SRL_I16;
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break;
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default:
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assert ( 0 && "This shift is not implemented yet.");
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return SDValue();
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}
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} else if (N->getValueType(0) == MVT::i32) {
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switch (N->getOpcode()) {
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case ISD::SRA:
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CallCode = PIC16ISD::SRA_I32;
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break;
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case ISD::SHL:
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CallCode = PIC16ISD::SLL_I32;
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break;
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case ISD::SRL:
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CallCode = PIC16ISD::SRL_I32;
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break;
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default:
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assert ( 0 && "This shift is not implemented yet.");
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return SDValue();
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}
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} else {
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//assert ( 0 && "Shift for this value type not yet implemented.");
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PIC16ISD::PIC16Libcall CallCode;
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switch (N->getOpcode()) {
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case ISD::SRA:
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CallCode = PIC16ISD::SRA_I8;
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break;
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case ISD::SHL:
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CallCode = PIC16ISD::SLL_I8;
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break;
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case ISD::SRL:
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CallCode = PIC16ISD::SRL_I8;
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break;
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default:
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assert ( 0 && "This shift is not implemented yet.");
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return SDValue();
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}
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SmallVector<SDValue, 2> Ops(2);
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Ops[0] = Value;
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Ops[1] = Amt;
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SDValue Call = MakePIC16LibCall(CallCode, N->getValueType(0), &Ops[0], 2, true, DAG);
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SDValue Call = MakePIC16Libcall(CallCode, N->getValueType(0), &Ops[0], 2, true, DAG);
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return Call;
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}
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void PIC16TargetLowering::LowerOperationWrapper(SDValue Op,
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SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG) {
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SDValue Res;
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unsigned i;
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS:
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Res = LowerFORMAL_ARGUMENTS(Op, DAG); break;
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case ISD::LOAD:
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Res = ExpandLoad(Op.getNode(), DAG); break;
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case ISD::CALL:
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Res = LowerCALL(Op, DAG); break;
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default: {
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// All other operations are handled in LowerOperation.
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Res = LowerOperation(Op, DAG);
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if (Res.getNode())
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Results.push_back(Res);
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return;
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}
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}
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SDNode *N = Res.getNode();
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unsigned NumValues = N->getNumValues();
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for (i=0; i< NumValues ; i++) {
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Results.push_back(SDValue(N, i));
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}
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}
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SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS:
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@ -815,14 +810,12 @@ SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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return ExpandShift(Op.getNode(), DAG);
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return LowerShift(Op, DAG);
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case ISD::OR:
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case ISD::AND:
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case ISD::XOR:
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return LowerBinOp(Op, DAG);
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case ISD::CALL:
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// This is called only from LegalizeDAG. No call is made to
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// legalize CALL node from LegalizeType.
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return LowerCALL(Op, DAG);
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case ISD::RET:
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return LowerRET(Op, DAG);
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@ -1142,6 +1135,9 @@ SDValue PIC16TargetLowering:: LowerADD(SDValue Op, SelectionDAG &DAG) {
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else
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return DAG.getNode(Op.getOpcode(), Tys, Op.getOperand(MemOp ^ 1), NewVal);
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}
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else if (Op.getOpcode() == ISD::ADD) {
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return Op;
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}
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else {
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return SDValue();
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}
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@ -1219,10 +1215,10 @@ static PIC16CC::CondCodes IntCCToPIC16CC(ISD::CondCode CC) {
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case ISD::SETGE: return PIC16CC::GE;
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case ISD::SETLT: return PIC16CC::LT;
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case ISD::SETLE: return PIC16CC::LE;
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case ISD::SETULT: return PIC16CC::LT;
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case ISD::SETULT: return PIC16CC::ULT;
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case ISD::SETULE: return PIC16CC::LE;
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case ISD::SETUGE: return PIC16CC::GE;
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case ISD::SETUGT: return PIC16CC::GT;
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case ISD::SETUGT: return PIC16CC::UGT;
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}
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}
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@ -1268,18 +1264,36 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS,
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case PIC16CC::GT:
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CondCode = PIC16CC::LT;
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break;
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case PIC16CC::ULT:
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CondCode = PIC16CC::UGT;
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break;
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case PIC16CC::UGT:
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CondCode = PIC16CC::ULT;
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break;
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case PIC16CC::GE:
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CondCode = PIC16CC::LE;
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break;
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case PIC16CC::LE:
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CondCode = PIC16CC::GE;
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break;
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case PIC16CC::ULE:
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CondCode = PIC16CC::UGE;
|
||||
break;
|
||||
case PIC16CC::UGE:
|
||||
CondCode = PIC16CC::ULE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
PIC16CC = DAG.getConstant(CondCode, MVT::i8);
|
||||
SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag);
|
||||
|
||||
// These are signed comparisons.
|
||||
SDValue Mask = DAG.getConstant(128, MVT::i8);
|
||||
if (isSignedComparison(CondCode)) {
|
||||
LHS = DAG.getNode (ISD::XOR, MVT::i8, LHS, Mask);
|
||||
RHS = DAG.getNode (ISD::XOR, MVT::i8, RHS, Mask);
|
||||
}
|
||||
// We can use a subtract operation to set the condition codes. But
|
||||
// we need to put one operand in memory if required.
|
||||
// Nothing to do if the first operand is already a direct load and it has
|
||||
|
|
|
@ -52,16 +52,11 @@ namespace llvm {
|
|||
RAM_SPACE = 0, // RAM address space
|
||||
ROM_SPACE = 1 // ROM address space number is 1
|
||||
};
|
||||
enum PIC16LibCall {
|
||||
enum PIC16Libcall {
|
||||
MUL_I8,
|
||||
SRA_I8,
|
||||
SLL_I8,
|
||||
SRL_I8,
|
||||
SRA_I16,
|
||||
SLL_I16,
|
||||
SRL_I16,
|
||||
SRA_I32,
|
||||
SLL_I32,
|
||||
SRL_I32,
|
||||
PIC16UnknownCall
|
||||
};
|
||||
}
|
||||
|
@ -79,8 +74,8 @@ namespace llvm {
|
|||
virtual const char *getTargetNodeName(unsigned Opcode) const;
|
||||
/// getSetCCResultType - Return the ISD::SETCC ValueType
|
||||
virtual MVT getSetCCResultType(MVT ValType) const;
|
||||
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
|
||||
SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG);
|
||||
SDValue LowerShift(SDValue Op, SelectionDAG &DAG);
|
||||
SDValue LowerADD(SDValue Op, SelectionDAG &DAG);
|
||||
SDValue LowerSUB(SDValue Op, SelectionDAG &DAG);
|
||||
SDValue LowerBinOp(SDValue Op, SelectionDAG &DAG);
|
||||
|
@ -98,15 +93,19 @@ namespace llvm {
|
|||
MachineBasicBlock *MBB);
|
||||
|
||||
|
||||
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
|
||||
virtual void ReplaceNodeResults(SDNode *N,
|
||||
SmallVectorImpl<SDValue> &Results,
|
||||
SelectionDAG &DAG);
|
||||
virtual void LowerOperationWrapper(SDValue Op,
|
||||
SmallVectorImpl<SDValue> &Results,
|
||||
SelectionDAG &DAG);
|
||||
|
||||
SDValue ExpandStore(SDNode *N, SelectionDAG &DAG);
|
||||
SDValue ExpandLoad(SDNode *N, SelectionDAG &DAG);
|
||||
//SDValue ExpandAdd(SDNode *N, SelectionDAG &DAG);
|
||||
SDValue ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG);
|
||||
SDValue ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG);
|
||||
SDValue ExpandShift(SDNode *N, SelectionDAG &DAG);
|
||||
SDValue ExpandFrameIndex(SDNode *N, SelectionDAG &DAG);
|
||||
|
||||
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
||||
|
@ -159,15 +158,15 @@ namespace llvm {
|
|||
|
||||
|
||||
// Extending the LIB Call framework of LLVM
|
||||
// To hold the names of PIC16LibCalls
|
||||
const char *PIC16LibCallNames[PIC16ISD::PIC16UnknownCall];
|
||||
// To hold the names of PIC16Libcalls
|
||||
const char *PIC16LibcallNames[PIC16ISD::PIC16UnknownCall];
|
||||
|
||||
// To set and retrieve the lib call names
|
||||
void setPIC16LibCallName(PIC16ISD::PIC16LibCall Call, const char *Name);
|
||||
const char *getPIC16LibCallName(PIC16ISD::PIC16LibCall Call);
|
||||
void setPIC16LibcallName(PIC16ISD::PIC16Libcall Call, const char *Name);
|
||||
const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call);
|
||||
|
||||
// Make PIC16 LibCall
|
||||
SDValue MakePIC16LibCall(PIC16ISD::PIC16LibCall Call, MVT RetVT,
|
||||
// Make PIC16 Libcall
|
||||
SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT,
|
||||
const SDValue *Ops, unsigned NumOps, bool isSigned,
|
||||
SelectionDAG &DAG);
|
||||
|
||||
|
|
|
@ -138,9 +138,8 @@ bool PIC16InstrInfo::copyRegToReg (MachineBasicBlock &MBB,
|
|||
}
|
||||
|
||||
bool PIC16InstrInfo::isMoveInstr(const MachineInstr &MI,
|
||||
unsigned &SrcReg, unsigned &DestReg,
|
||||
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
|
||||
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
|
||||
unsigned &SrcReg,
|
||||
unsigned &DestReg) const {
|
||||
|
||||
if (MI.getOpcode() == PIC16::copy_fsr
|
||||
|| MI.getOpcode() == PIC16::copy_w) {
|
||||
|
|
|
@ -61,8 +61,8 @@ public:
|
|||
const TargetRegisterClass *DestRC,
|
||||
const TargetRegisterClass *SrcRC) const;
|
||||
virtual bool isMoveInstr(const MachineInstr &MI,
|
||||
unsigned &SrcReg, unsigned &DstReg,
|
||||
unsigned &SrcSubIdx, unsigned &DstSubIdx) const;
|
||||
unsigned &SrcReg,
|
||||
unsigned &DestReg) const;
|
||||
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in New Issue