[mips] Refactor conditional branch instructions with two register operands.
Separate encoding information from the rest. llvm-svn: 170657
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@ -166,8 +166,8 @@ def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>,
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/// Jump and Branch Instructions
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def JR64 : IndirectBranch<CPU64Regs>;
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def BEQ64 : CBranch<0x04, "beq", seteq, CPU64Regs>;
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def BNE64 : CBranch<0x05, "bne", setne, CPU64Regs>;
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def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<0x01, 1, "bgez", setge, CPU64Regs>;
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def BGTZ64 : CBranchZero<0x07, 0, "bgtz", setgt, CPU64Regs>;
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def BLEZ64 : CBranchZero<0x06, 0, "blez", setle, CPU64Regs>;
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@ -252,6 +252,19 @@ class SRLV_FM<bits<6> funct, bit rotate> {
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let Inst{5-0} = funct;
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}
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class BEQ_FM<bits<6> op> {
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bits<5> rs;
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bits<5> rt;
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bits<16> offset;
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bits<32> Inst;
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let Inst{31-26} = op;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-0} = offset;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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@ -545,10 +545,11 @@ multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
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}
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// Conditional Branch
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class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
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BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
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!strconcat(instr_asm, "\t$rs, $rt, $imm16"),
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[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
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class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
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InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
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!strconcat(opstr, "\t$rs, $rt, $offset"),
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[(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
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FrmI> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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@ -996,8 +997,8 @@ def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
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Requires<[RelocStatic, HasStdEnc]>, IsBranch;
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def JR : IndirectBranch<CPURegs>;
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def B : UncondBranch<0x04, "b">;
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def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
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def BNE : CBranch<0x05, "bne", setne, CPURegs>;
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def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
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def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
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def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
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def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
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def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
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