[Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trap

The trap instruction is intercepted by various runtime environments,
and instead of a crash it creates confusion.

This reapplies r354606 with a fix.

llvm-svn: 354611
This commit is contained in:
Krzysztof Parzyszek 2019-02-21 19:42:39 +00:00
parent 0ee7bd4ac5
commit f6e875bacf
5 changed files with 61 additions and 2 deletions

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@ -1313,6 +1313,38 @@ bool HexagonInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
return true; return true;
} }
case Hexagon::PS_crash: {
// Generate a misaligned load that is guaranteed to cause a crash.
class CrashPseudoSourceValue : public PseudoSourceValue {
public:
CrashPseudoSourceValue(const TargetInstrInfo &TII)
: PseudoSourceValue(TargetCustom, TII) {}
bool isConstant(const MachineFrameInfo *) const override {
return false;
}
bool isAliased(const MachineFrameInfo *) const override {
return false;
}
bool mayAlias(const MachineFrameInfo *) const override {
return false;
}
void printCustom(raw_ostream &OS) const override {
OS << "MisalignedCrash";
}
};
static const CrashPseudoSourceValue CrashPSV(*this);
MachineMemOperand *MMO = MF.getMachineMemOperand(
MachinePointerInfo(&CrashPSV),
MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 8, 1);
BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
.addImm(0xBADC0FEE) // Misaligned load.
.addMemOperand(MMO);
MBB.erase(MI);
return true;
}
case Hexagon::PS_tailcall_i: case Hexagon::PS_tailcall_i:
MI.setDesc(get(Hexagon::J2_jump)); MI.setDesc(get(Hexagon::J2_jump));
return true; return true;

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@ -3081,7 +3081,7 @@ def: Pat<(HexagonALLOCA I32:$Rs, (i32 imm:$A)),
def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>; def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
def: Pat<(HexagonBARRIER), (Y2_barrier)>; def: Pat<(HexagonBARRIER), (Y2_barrier)>;
def: Pat<(trap), (J2_trap0 (i32 0))>; def: Pat<(trap), (PS_crash)>;
// Read cycle counter. // Read cycle counter.
def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>; def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;

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@ -559,3 +559,8 @@ defm PS_storerh : NewCircularStore<IntRegs, HalfWordAccess>;
defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>; defm PS_storerf : NewCircularStore<IntRegs, HalfWordAccess>;
defm PS_storeri : NewCircularStore<IntRegs, WordAccess>; defm PS_storeri : NewCircularStore<IntRegs, WordAccess>;
defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>; defm PS_storerd : NewCircularStore<DoubleRegs, WordAccess>;
// A pseudo that generates a runtime crash. This is used to implement
// __builtin_trap.
let hasSideEffects = 1, isPseudo = 1, isCodeGenOnly = 1, isSolo = 1 in
def PS_crash: InstHexagon<(outs), (ins), "", [], "", PSEUDO, TypePSEUDO>;

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@ -0,0 +1,20 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Generate code that is guaranteed to crash. At the moment, it's a
; misaligned load.
; CHECK: memd(##3134984174)
target triple = "hexagon"
; Function Attrs: noreturn nounwind
define i32 @f0() #0 {
entry:
tail call void @llvm.trap()
unreachable
}
; Function Attrs: cold noreturn nounwind
declare void @llvm.trap() #1
attributes #0 = { noreturn nounwind "target-cpu"="hexagonv60" }
attributes #1 = { cold noreturn nounwind }

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@ -1,5 +1,7 @@
; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s ; RUN: llc -march=hexagon -trap-unreachable < %s | FileCheck %s
; CHECK: trap
; Trap is implemented via a misaligned load.
; CHECK: memd(##3134984174)
define void @fred() #0 { define void @fred() #0 {
unreachable unreachable