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R600/SI: Fix size of VReg_1 

This is really a 32-bit register, if we try to check the size of it,
we want 32-bits.

llvm-svn: 229223
This commit is contained in:
Matt Arsenault 2015-02-14 02:51:44 +00:00
parent 8480c87ce6
commit f417ff8f2a
1 changed files with 1 additions and 1 deletions
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llvm/lib/Target/R600/SIRegisterInfo.td
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@ -209,7 +209,7 @@ def VReg_256 : RegisterClass<"AMDGPU", [v32i8, v8i32, v8f32], 256, (add VGPR_256
def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>; def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 512, (add VGPR_512)>;
def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)>; def VReg_1 : RegisterClass<"AMDGPU", [i1, i32], 32, (add VGPR_32)>;
class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> { class RegImmOperand <RegisterClass rc> : RegisterOperand<rc> {
let OperandNamespace = "AMDGPU"; let OperandNamespace = "AMDGPU";