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Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane 

This should eliminate most uses of countPopulation and Log2_32 on
the lane mask values.

llvm-svn: 308658
This commit is contained in:
Krzysztof Parzyszek 2017-07-20 19:43:19 +00:00
parent 27c12e088e
commit f3a778d757
5 changed files with 14 additions and 12 deletions
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7
llvm/include/llvm/MC/LaneBitmask.h
View File

@ -73,6 +73,13 @@ namespace llvm {
constexpr Type getAsInteger() const { return Mask; }
unsigned getNumLanes() const {
return countPopulation(Mask);
}
unsigned getHighestLane() const {
return Log2_32(Mask);
}
static LaneBitmask getNone() { return LaneBitmask(0); }
static LaneBitmask getAll() { return ~LaneBitmask(0); }
static LaneBitmask getLane(unsigned Lane) {

6
llvm/lib/CodeGen/SplitKit.cpp
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@ -552,7 +552,7 @@ SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg,
if ((SubRegMask & ~LaneMask).any())
continue;
unsigned PopCount = countPopulation(SubRegMask.getAsInteger());
unsigned PopCount = SubRegMask.getNumLanes();
PossibleIndexes.push_back(Idx);
if (PopCount > BestCover) {
BestCover = PopCount;
@ -583,8 +583,8 @@ SlotIndex SplitEditor::buildCopy(unsigned FromReg, unsigned ToReg,
// Try to cover as much of the remaining lanes as possible but
// as few of the already covered lanes as possible.
int Cover = countPopulation((SubRegMask & LanesLeft).getAsInteger())
- countPopulation((SubRegMask & ~LanesLeft).getAsInteger());
int Cover = (SubRegMask & LanesLeft).getNumLanes()
- (SubRegMask & ~LanesLeft).getNumLanes();
if (Cover > BestCover) {
BestCover = Cover;
BestIdx = Idx;

2
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
View File

@ -107,7 +107,7 @@ void GCNRegPressure::inc(unsigned Reg,
assert(PrevMask < NewMask);
Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] +=
Sign * countPopulation((~PrevMask & NewMask).getAsInteger());
Sign * (~PrevMask & NewMask).getNumLanes();
if (PrevMask.none()) {
assert(NewMask.any());

3
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -1275,8 +1275,7 @@ const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
return RC;
// We can assume that each lane corresponds to one 32-bit register.
LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger();
unsigned Count = countPopulation(Mask);
unsigned Count = getSubRegIndexLaneMask(SubIdx).getNumLanes();
if (isSGPRClass(RC)) {
switch (Count) {
case 1:

8
llvm/utils/TableGen/CodeGenRegisters.cpp
View File

@ -1295,9 +1295,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
// Moving from a class with no subregisters we just had a single lane:
// The subregister must be a leaf subregister and only occupies 1 bit.
// Move the bit from the class without subregisters into that position.
static_assert(sizeof(Idx.LaneMask.getAsInteger()) == 4,
"Change Log2_32 to a proper one");
unsigned DstBit = Log2_32(Idx.LaneMask.getAsInteger());
unsigned DstBit = Idx.LaneMask.getHighestLane();
assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
"Must be a leaf subregister");
MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
@ -1328,9 +1326,7 @@ void CodeGenRegBank::computeSubRegLaneMasks() {
assert(Composite->getComposites().empty());
// Create Mask+Rotate operation and merge with existing ops if possible.
static_assert(sizeof(Composite->LaneMask.getAsInteger()) == 4,
"Change Log2_32 to a proper one");
unsigned DstBit = Log2_32(Composite->LaneMask.getAsInteger());
unsigned DstBit = Composite->LaneMask.getHighestLane();
int Shift = DstBit - SrcBit;
uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
: LaneBitmask::BitWidth + Shift;