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Add operand cycles for vldr / vstr. 

llvm-svn: 115353
This commit is contained in:
Evan Cheng 2010-10-01 21:40:30 +00:00
parent bf73fe5e8d
commit f3179567de
2 changed files with 17 additions and 8 deletions
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12
llvm/lib/Target/ARM/ARMScheduleA8.td
View File

@ -384,7 +384,8 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A8_Issue], 0>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0], 0>,
InstrStage<1, [A8_NLSPipe]>]>,
InstrStage<1, [A8_NLSPipe]>],
[2, 1]>,
//
// Double-precision FP Load
// use A8_Issue to enforce the 1 load/store per cycle limit
@ -393,7 +394,8 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrStage<1, [A8_Pipe1]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0], 0>,
InstrStage<1, [A8_NLSPipe]>]>,
InstrStage<1, [A8_NLSPipe]>],
[2, 1]>,
//
// FP Load Multiple
// use A8_Issue to enforce the 1 load/store per cycle limit
@ -409,7 +411,8 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrItinData<IIC_fpStore32,[InstrStage<1, [A8_Issue], 0>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0], 0>,
InstrStage<1, [A8_NLSPipe]>]>,
InstrStage<1, [A8_NLSPipe]>],
[1, 1]>,
//
// Double-precision FP Store
// use A8_Issue to enforce the 1 load/store per cycle limit
@ -418,7 +421,8 @@ def CortexA8Itineraries : ProcessorItineraries<
InstrStage<1, [A8_Pipe1]>,
InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
InstrStage<1, [A8_LdSt0], 0>,
InstrStage<1, [A8_NLSPipe]>]>,
InstrStage<1, [A8_NLSPipe]>],
[1, 1]>,
//
// FP Store Multiple
// use A8_Issue to enforce the 1 load/store per cycle limit

13
llvm/lib/Target/ARM/ARMScheduleA9.td
View File

@ -482,13 +482,16 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrItinData<IIC_fpLoad32, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_Pipe1], 0>,
InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
InstrStage<1, [A9_MUX0, A9_NPipe]>],
[1, 1]>,
//
// Double-precision FP Load
// FIXME: Result latency is 1 if address is 64-bit aligned.
InstrItinData<IIC_fpLoad64, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_Pipe1], 0>,
InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
InstrStage<1, [A9_MUX0, A9_NPipe]>],
[2, 1]>,
//
// FP Load Multiple
InstrItinData<IIC_fpLoadm, [InstrStage<1, [A9_DRegsVFP], 0, Required>,
@ -500,13 +503,15 @@ def CortexA9Itineraries : ProcessorItineraries<
InstrItinData<IIC_fpStore32,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_Pipe1], 0>,
InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
InstrStage<1, [A9_MUX0, A9_NPipe]>],
[1, 1]>,
//
// Double-precision FP Store
InstrItinData<IIC_fpStore64,[InstrStage<1, [A9_DRegsVFP], 0, Required>,
InstrStage<2, [A9_DRegsN], 0, Reserved>,
InstrStage<1, [A9_Pipe1], 0>,
InstrStage<1, [A9_MUX0, A9_NPipe]>]>,
InstrStage<1, [A9_MUX0, A9_NPipe]>],
[1, 1]>,
//
// FP Store Multiple
InstrItinData<IIC_fpStorem, [InstrStage<1, [A9_DRegsVFP], 0, Required>,