[ARM] Add support for MVE vaddv
This patch adds vecreduce_add and the relevant instruction selection for vaddv. Differential revision: https://reviews.llvm.org/D66085 llvm-svn: 369245
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@ -239,6 +239,9 @@ def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
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def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
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SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
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]>;
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def SDTVecReduce : SDTypeProfile<1, 1, [ // vector reduction
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SDTCisInt<0>, SDTCisVec<1>
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]>;
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def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
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SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
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@ -415,6 +418,8 @@ def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
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def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
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def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
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def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
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def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
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def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
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def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
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@ -267,6 +267,9 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
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setOperationAction(ISD::SREM, VT, Expand);
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setOperationAction(ISD::CTPOP, VT, Expand);
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// Vector reductions
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setOperationAction(ISD::VECREDUCE_ADD, VT, Legal);
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if (!HasMVEFP) {
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setOperationAction(ISD::SINT_TO_FP, VT, Expand);
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setOperationAction(ISD::UINT_TO_FP, VT, Expand);
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@ -549,6 +549,12 @@ defm MVE_VADDVu8 : MVE_VADDV_A<"u8", 0b1, 0b00>;
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defm MVE_VADDVu16 : MVE_VADDV_A<"u16", 0b1, 0b01>;
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defm MVE_VADDVu32 : MVE_VADDV_A<"u32", 0b1, 0b10>;
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let Predicates = [HasMVEInt] in {
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def : Pat<(i32 (vecreduce_add (v4i32 MQPR:$src))), (i32 (MVE_VADDVu32no_acc $src))>;
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def : Pat<(i32 (vecreduce_add (v8i16 MQPR:$src))), (i32 (MVE_VADDVu16no_acc $src))>;
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def : Pat<(i32 (vecreduce_add (v16i8 MQPR:$src))), (i32 (MVE_VADDVu8no_acc $src))>;
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}
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class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
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bit A, bit U, list<dag> pattern=[]>
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: MVE_rDest<(outs tGPREven:$RdaLo, tGPROdd:$RdaHi), iops, NoItinerary, iname,
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@ -1044,3 +1044,28 @@ void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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if (Cost < 12)
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UP.Force = true;
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}
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bool ARMTTIImpl::useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const {
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assert(isa<VectorType>(Ty) && "Expected Ty to be a vector type");
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unsigned ScalarBits = Ty->getScalarSizeInBits();
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if (!ST->hasMVEIntegerOps())
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return false;
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switch (Opcode) {
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case Instruction::FAdd:
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case Instruction::FMul:
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case Instruction::And:
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case Instruction::Or:
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case Instruction::Xor:
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case Instruction::Mul:
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case Instruction::ICmp:
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case Instruction::FCmp:
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return false;
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case Instruction::Add:
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return ScalarBits * Ty->getVectorNumElements() == 128;
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default:
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llvm_unreachable("Unhandled reduction opcode");
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}
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return false;
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}
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@ -156,6 +156,13 @@ public:
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int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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bool useReductionIntrinsic(unsigned Opcode, Type *Ty,
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TTI::ReductionFlags Flags) const;
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bool shouldExpandReduction(const IntrinsicInst *II) const {
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return false;
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}
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int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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const Instruction *I = nullptr);
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@ -0,0 +1,34 @@
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp %s -o - | FileCheck %s
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declare i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32>)
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define arm_aapcs_vfpcc i32 @vaddv_v4i32_i32(<4 x i32> %s1) {
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; CHECK-LABEL: vaddv_v4i32_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u32 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i32 @llvm.experimental.vector.reduce.add.i32.v4i32(<4 x i32> %s1)
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ret i32 %r
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}
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declare i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16>)
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define arm_aapcs_vfpcc i16 @vaddv_v16i16_i16(<8 x i16> %s1) {
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; CHECK-LABEL: vaddv_v16i16_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u16 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i16 @llvm.experimental.vector.reduce.add.i16.v8i16(<8 x i16> %s1)
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ret i16 %r
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}
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declare i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8>)
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define arm_aapcs_vfpcc i8 @vaddv_v16i8_i8(<16 x i8> %s1) {
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; CHECK-LABEL: vaddv_v16i8_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vaddv.u8 r0, q0
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; CHECK-NEXT: bx lr
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entry:
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%r = call i8 @llvm.experimental.vector.reduce.add.i8.v16i8(<16 x i8> %s1)
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ret i8 %r
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}
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