replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

ScheduleDAGInstrs: Ignore dependencies of constant physregs 

There is no need to track dependencies for constant physregs, as they
don't change their value no matter in what order you read/write to them.

Differential Revision: https://reviews.llvm.org/D26221

llvm-svn: 286526
This commit is contained in:
Matthias Braun 2016-11-10 23:46:44 +00:00
parent ff82547f98
commit f29b12dca8
4 changed files with 35 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -323,6 +323,9 @@ void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
MachineInstr *MI = SU->getInstr();
MachineOperand &MO = MI->getOperand(OperIdx);
unsigned Reg = MO.getReg();
// We do not need to track any dependencies for constant registers.
if (MRI.isConstantPhysReg(Reg))
return;
// Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue

4
llvm/test/CodeGen/AArch64/machine_cse_impdef_killflags.ll
View File

@ -8,8 +8,8 @@ define i64 @csed-impdef-killflag(i64 %a) {
; CHECK-DAG: orr [[REG1:w[0-9]+]], wzr, #0x1
; CHECK-DAG: orr [[REG2:x[0-9]+]], xzr, #0x2
; CHECK-DAG: orr [[REG3:x[0-9]+]], xzr, #0x3
; CHECK: cmp x0, #0
; CHECK-DAG: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
; CHECK-DAG: cmp x0, #0
; CHECK: csel w[[SELECT_WREG_1:[0-9]+]], wzr, [[REG1]], ne
; CHECK-DAG: csel [[SELECT_XREG_2:x[0-9]+]], [[REG2]], [[REG3]], ne
; CHECK: ubfx [[SELECT_XREG_1:x[0-9]+]], x[[SELECT_WREG_1]], #0, #32
; CHECK-NEXT: add x0, [[SELECT_XREG_2]], [[SELECT_XREG_1]]

29
llvm/test/CodeGen/AArch64/scheduledag-constreg.mir Normal file
View File

@ -0,0 +1,29 @@
# RUN: llc -o /dev/null %s -mtriple=aarch64-- -run-pass=machine-scheduler -enable-misched -debug-only=misched 2>&1 | FileCheck %s
# REQUIRES: asserts
--- |
define void @func() { ret void }
...
---
# Check that the instructions are not dependent on each other, even though
# they all read/write to the zero register.
# CHECK-LABEL: MI Scheduling
# CHECK: SU(0): %WZR<def,dead> = SUBSWri %W1, 0, 0, %NZCV<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(1): %W2<def> = COPY %WZR
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(2): %WZR<def,dead> = SUBSWri %W3, 0, 0, %NZCV<imp-def,dead>
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
# CHECK: SU(3): %W4<def> = COPY %WZR
# CHECK: # succs left : 0
# CHECK-NOT: Successors:
name: func
body: |
bb.0:
dead %wzr = SUBSWri %w1, 0, 0, implicit-def dead %nzcv
%w2 = COPY %wzr
dead %wzr = SUBSWri %w3, 0, 0, implicit-def dead %nzcv
%w4 = COPY %wzr
...

2
llvm/test/CodeGen/AArch64/subs-to-sub-opt.ll
View File

@ -7,7 +7,7 @@
define i32 @test01() nounwind {
; CHECK: ldrb {{.*}}
; CHECK-NEXT: ldrb {{.*}}
; CHECK-NEXT: sub {{.*}}
; CHECK: sub {{.*}}
; CHECK-NEXT: cmn {{.*}}
entry:
%0 = load i8, i8* @a, align 1