[mips] Marked up instructions added in MIPS-III and tested that IAS for -mcpu=mips[12] does not accept them
Summary: This required a new instruction group representing the 32-bit subset of MIPS-III that was available in MIPS32 A small number of instructions are correctly rejected but with the wrong error message. These have been placed in a separate test for now. There's some obvious InstAlias's that ought to be marked MIPS-III but arent. This is because they are not currently tested. I intend to catch these with a final pass through the tablegen records to find tablegen records without ISA annotations. Depends on D3674 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3675 llvm-svn: 208408
This commit is contained in:
Daniel Sanders
parent
826b5adb6c
commit
f2056bef32
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@ -90,10 +90,23 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
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def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
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"Mips II ISA Support [highly experimental]",
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[FeatureMips1]>;
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def FeatureMips3_32 : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
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"Subset of MIPS-III that is also in MIPS32 "
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"[highly experimental]">;
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureMips3_32,
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FeatureGP64Bit, FeatureFP64Bit]>;
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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[FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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[FeatureMips4]>;
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def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
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"Mips32 ISA Support",
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[FeatureMips2, FeatureCondMov,
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FeatureBitCount]>;
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[FeatureMips2, FeatureMips3_32,
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FeatureCondMov, FeatureBitCount]>;
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def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
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"Mips32r2", "Mips32r2 ISA Support",
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[FeatureMips32, FeatureSEInReg, FeatureSwap,
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@ -103,18 +116,6 @@ def FeatureMips32r6 : SubtargetFeature<"mips32r6", "MipsArchVersion",
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"Mips32r6 ISA Support [experimental]",
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[FeatureMips32r2, FeatureFP64Bit,
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FeatureNaN2008]>;
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// FIXME: Need to check whether FPIdx belongs in the MIPS-III or MIPS-IV Implies
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// list but for now it doesn't matter since FPIdx isn't actually attached
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// to any instructions.
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def FeatureMips3 : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
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"MIPS III ISA Support [highly experimental]",
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[FeatureMips2, FeatureGP64Bit, FeatureFP64Bit]>;
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def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
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"Mips4", "MIPS IV ISA Support",
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[FeatureMips3, FeatureFPIdx, FeatureCondMov]>;
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def FeatureMips5 : SubtargetFeature<"mips5", "MipsArchVersion", "Mips5",
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"MIPS V ISA Support [highly experimental]",
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[FeatureMips4]>;
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def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
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"Mips64", "Mips64 ISA Support",
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[FeatureMips5, FeatureMips32, FeatureFPIdx]>;
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@ -61,10 +61,11 @@ let isPseudo = 1, isCodeGenOnly = 1 in {
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//===----------------------------------------------------------------------===//
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let DecoderNamespace = "Mips64" in {
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/// Arithmetic Instructions (ALU Immediate)
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>,
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ISA_MIPS3;
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def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
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immSExt16, add>,
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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ADDI_FM<0x19>, IsAsCheapAsAMove, ISA_MIPS3;
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let isCodeGenOnly = 1 in {
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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@ -81,12 +82,14 @@ def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
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}
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/// Arithmetic Instructions (3-Operand, R-Type)
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def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>;
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
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ADD_FM<0, 0x2d>;
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
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ADD_FM<0, 0x2f>;
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def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>;
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def DADD : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>, ADD_FM<0, 0x2c>,
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ISA_MIPS3;
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>, ADD_FM<0, 0x2d>,
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ISA_MIPS3;
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
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ISA_MIPS3;
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def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
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ISA_MIPS3;
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let isCodeGenOnly = 1 in {
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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@ -99,23 +102,23 @@ def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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/// Shift Instructions
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def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
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SRA_FM<0x38, 0>;
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SRA_FM<0x38, 0>, ISA_MIPS3;
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def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
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SRA_FM<0x3a, 0>;
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SRA_FM<0x3a, 0>, ISA_MIPS3;
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def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
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SRA_FM<0x3b, 0>;
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SRA_FM<0x3b, 0>, ISA_MIPS3;
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def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
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SRLV_FM<0x14, 0>;
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SRLV_FM<0x14, 0>, ISA_MIPS3;
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def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
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SRLV_FM<0x16, 0>;
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SRLV_FM<0x16, 0>, ISA_MIPS3;
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def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
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SRLV_FM<0x17, 0>;
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SRLV_FM<0x17, 0>, ISA_MIPS3;
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def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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SRA_FM<0x3c, 0>;
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SRA_FM<0x3c, 0>, ISA_MIPS3;
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def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
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SRA_FM<0x3e, 0>;
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SRA_FM<0x3e, 0>, ISA_MIPS3;
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def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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SRA_FM<0x3f, 0>;
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SRA_FM<0x3f, 0>, ISA_MIPS3;
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// Rotate Instructions
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def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
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@ -139,9 +142,9 @@ def SH64 : Store<"sh", GPR64Opnd, truncstorei16, II_SH>, LW_FM<0x29>;
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def SW64 : Store<"sw", GPR64Opnd, truncstorei32, II_SW>, LW_FM<0x2b>;
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}
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def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>;
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def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>;
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def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>;
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def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>, ISA_MIPS3;
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def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>, ISA_MIPS3;
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def SD : Store<"sd", GPR64Opnd, store, II_SD>, LW_FM<0x3f>, ISA_MIPS3;
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/// load/store left/right
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let isCodeGenOnly = 1 in {
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@ -151,14 +154,18 @@ def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, II_SWL>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, II_SWR>, LW_FM<0x2e>;
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}
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def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>;
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def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>;
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def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>,
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ISA_MIPS3;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>,
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ISA_MIPS3;
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def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, II_SDL>, LW_FM<0x2c>,
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ISA_MIPS3;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, II_SDR>, LW_FM<0x2d>,
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ISA_MIPS3;
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/// Load-linked, Store-conditional
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def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
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def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
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def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>, ISA_MIPS3;
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def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>, ISA_MIPS3;
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/// Jump and Branch Instructions
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let isCodeGenOnly = 1 in {
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@ -176,17 +183,17 @@ def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
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/// Multiply and Divide Instructions.
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def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1c>;
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MULT_FM<0, 0x1c>, ISA_MIPS3;
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def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1d>;
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MULT_FM<0, 0x1d>, ISA_MIPS3;
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def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
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II_DMULT>;
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def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
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II_DMULTU>;
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def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1e>;
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MULT_FM<0, 0x1e>, ISA_MIPS3;
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def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
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MULT_FM<0, 0x1f>;
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MULT_FM<0, 0x1f>, ISA_MIPS3;
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def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
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II_DDIV, 0, 1, 1>;
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def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
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@ -440,7 +447,8 @@ def : MipsInstAlias<"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
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0>;
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def : MipsInstAlias<"dsll $rd, $rt, $rs",
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(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
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def : MipsInstAlias<"dsubu $rt, $rs, $imm",
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(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
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InvertedImOperand64:$imm), 0>;
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@ -453,16 +461,18 @@ def : MipsInstAlias<"dsubu $rs, $imm",
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InvertedImOperand64:$imm),
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0>;
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def : MipsInstAlias<"dsra $rd, $rt, $rs",
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(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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(DSRAV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
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def : MipsInstAlias<"dsrl $rd, $rt, $rs",
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
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ISA_MIPS3;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
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def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
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def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
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def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>, ISA_MIPS3;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>, ISA_MIPS3;
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def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>, ISA_MIPS3;
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}
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// Two operand (implicit 0 selector) versions:
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@ -298,9 +298,9 @@ let DecoderNamespace = "Mips64" in {
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def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x20, 20>;
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def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x25, 16>;
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ABSS_FM<0x25, 16>, INSN_MIPS3_32;
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x25, 17>;
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ABSS_FM<0x25, 17>, INSN_MIPS3_32;
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>, FGR_32;
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@ -358,9 +358,9 @@ def MFHC1 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, FGRH32Opnd, II_MFHC1>,
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def MTHC1 : MMRel, MTC1_FT<"mthc1", FGRH32Opnd, GPR32Opnd, II_MTHC1>,
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MFC1_FM<7>;
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def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,
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bitconvert>, MFC1_FM<1>;
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bitconvert>, MFC1_FM<1>, ISA_MIPS3;
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def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
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bitconvert>, MFC1_FM<5>;
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bitconvert>, MFC1_FM<5>, ISA_MIPS3;
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def FMOV_S : MMRel, ABSS_FT<"mov.s", FGR32Opnd, FGR32Opnd, II_MOV_S>,
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ABSS_FM<0x6, 16>;
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@ -158,6 +158,10 @@ def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
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AssemblerPredicate<"FeatureFPIdx">;
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def HasMips2 : Predicate<"Subtarget.hasMips2()">,
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AssemblerPredicate<"FeatureMips2">;
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def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
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AssemblerPredicate<"FeatureMips3_32">;
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def HasMips3 : Predicate<"Subtarget.hasMips3()">,
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AssemblerPredicate<"FeatureMips3">;
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def HasMips32 : Predicate<"Subtarget.hasMips32()">,
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AssemblerPredicate<"FeatureMips32">;
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def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
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@ -209,9 +213,13 @@ class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
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//===----------------------------------------------------------------------===//
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class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
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class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
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class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
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class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
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// The portions of MIPS-III that were also added to MIPS32
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class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
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class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
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class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
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@ -1069,7 +1077,7 @@ def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
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def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
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def TRAP : TrapBase<BREAK>;
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def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
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def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
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def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
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def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
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@ -80,12 +80,12 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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IsFP64bit(false), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false),
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HasCnMips(false), IsLinux(true), HasSEInReg(false), HasCondMov(false),
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HasSwap(false), HasBitCount(false), HasFPIdx(false), InMips16Mode(false),
|
||||
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
|
||||
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
|
||||
HasMSA(false), RM(_RM), OverrideMode(NoOverride), TM(_TM),
|
||||
TargetTriple(TT) {
|
||||
HasCnMips(false), IsLinux(true), HasMips3_32(false), HasSEInReg(false),
|
||||
HasCondMov(false), HasSwap(false), HasBitCount(false), HasFPIdx(false),
|
||||
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
|
||||
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
|
||||
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
|
||||
RM(_RM), OverrideMode(NoOverride), TM(_TM), TargetTriple(TT) {
|
||||
std::string CPUName = CPU;
|
||||
CPUName = selectMipsCPU(TT, CPUName);
|
||||
|
||||
|
|
|
|||
|
|
@ -79,6 +79,9 @@ protected:
|
|||
|
||||
/// Features related to the presence of specific instructions.
|
||||
|
||||
// HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
|
||||
bool HasMips3_32;
|
||||
|
||||
// HasSEInReg - SEB and SEH (signext in register) instructions.
|
||||
bool HasSEInReg;
|
||||
|
||||
|
|
@ -155,6 +158,7 @@ public:
|
|||
void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
|
||||
|
||||
bool hasMips2() const { return MipsArchVersion >= Mips2; }
|
||||
bool hasMips3() const { return MipsArchVersion >= Mips3; }
|
||||
bool hasMips32() const { return MipsArchVersion >= Mips32; }
|
||||
bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
|
||||
MipsArchVersion == Mips64r2; }
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
# Instructions that are invalid and are correctly rejected but use the wrong
|
||||
# error message at the moment.
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldc1 $f11,16391($s0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldr $14,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ll $v0,-7321($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sc $15,18904($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sd $12,5835($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdc1 $f31,30574($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdc2 $20,23157($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,65 @@
|
|||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips1 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
dmult $s7,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsub $a3,$s6,$8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ceil.w.s $f6,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmfc1 $12,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsllv $zero,$s4,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrlv $s3,$14,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.w.d $f14,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.w.s $f8,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.w.d $f6,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
tgeiu $sp,-28621 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
tlti $14,-21059 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
tltiu $ra,-5076 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
tnei $12,-29647 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.w.d $f22,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.w.s $f28,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
|
|
@ -0,0 +1,19 @@
|
|||
# Instructions that are invalid and are correctly rejected but use the wrong
|
||||
# error message at the moment.
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
dmult $s7,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
dsub $a3,$s6,$a4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ld $sp,-28645($s1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldl $t8,-4167($t8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
ldr $t2,-30358($s4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lld $zero,-14736($ra) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
scd $t3,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sd $t0,5835($a6) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
sdr $a7,-20423($t0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
# Instructions that are invalid
|
||||
#
|
||||
# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips2 \
|
||||
# RUN: 2>%t1
|
||||
# RUN: FileCheck %s < %t1
|
||||
|
||||
.set noat
|
||||
ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
cvt.s.l $f15,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddi $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddiu $k0,$s6,-4586 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ddiv $zero,$k0,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
ddivu $zero,$s0,$s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmfc1 $t0,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmtc1 $s0,$f14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dmultu $a1,$a2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,$s4,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll32 $zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsll32 $zero,$zero,18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsllv $zero,$s4,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra32 $gp,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsra32 $gp,$s2,10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrav $gp,$s2,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl $s3,$6,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl32 $s3,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrl32 $s3,$6,23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsrlv $s3,$t2,$s4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
dsubu $a1,$a1,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
eret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.l.d $f26,$f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
floor.l.s $f12,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.l.d $f12,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
round.l.s $f25,$f5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
||||
Loading…
Reference in New Issue