replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

MachineFunction: Return reference from getFunction(); NFC 

The Function can never be nullptr so we can return a reference.

llvm-svn: 320884
This commit is contained in:
Matthias Braun 2017-12-15 22:22:58 +00:00
parent 8539edb0f3
commit f1caa2833f
242 changed files with 829 additions and 843 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
View File

@ -1341,7 +1341,7 @@ raw_ostream &BlockFrequencyInfoImpl<BT>::print(raw_ostream &OS) const {
<< ", int = " << getBlockFreq(&BB).getFrequency();
if (Optional<uint64_t> ProfileCount =
BlockFrequencyInfoImplBase::getBlockProfileCount(
*F->getFunction(), getNode(&BB)))
F->getFunction(), getNode(&BB)))
OS << ", count = " << ProfileCount.getValue();
if (Optional<uint64_t> IrrLoopHeaderWeight =
BB.getIrrLoopHeaderWeight())

4
llvm/include/llvm/CodeGen/MachineFunction.h
View File

@ -380,8 +380,8 @@ public:
/// Return the DataLayout attached to the Module associated to this MF.
const DataLayout &getDataLayout() const;
/// getFunction - Return the LLVM function that this machine code represents
const Function *getFunction() const { return &F; }
/// Return the LLVM function that this machine code represents
const Function &getFunction() const { return F; }
/// getName - Return the name of the corresponding LLVM function.
StringRef getName() const;

10
llvm/include/llvm/CodeGen/MachineOptimizationRemarkEmitter.h
View File

@ -33,7 +33,7 @@ public:
const DiagnosticLocation &Loc,
const MachineBasicBlock *MBB)
: DiagnosticInfoOptimizationBase(Kind, DS_Remark, PassName, RemarkName,
*MBB->getParent()->getFunction(), Loc),
MBB->getParent()->getFunction(), Loc),
MBB(MBB) {}
/// MI-specific kinds of diagnostic Arguments.
@ -159,8 +159,8 @@ public:
/// (1) to filter trivial false positives or (2) to provide more context so
/// that non-trivial false positives can be quickly detected by the user.
bool allowExtraAnalysis(StringRef PassName) const {
return (MF.getFunction()->getContext().getDiagnosticsOutputFile() ||
MF.getFunction()->getContext()
return (MF.getFunction().getContext().getDiagnosticsOutputFile() ||
MF.getFunction().getContext()
.getDiagHandlerPtr()->isAnyRemarkEnabled(PassName));
}
@ -172,8 +172,8 @@ public:
// remarks enabled. We can't currently check whether remarks are requested
// for the calling pass since that requires actually building the remark.
if (MF.getFunction()->getContext().getDiagnosticsOutputFile() ||
MF.getFunction()->getContext().getDiagHandlerPtr()->isAnyRemarkEnabled()) {
if (MF.getFunction().getContext().getDiagnosticsOutputFile() ||
MF.getFunction().getContext().getDiagHandlerPtr()->isAnyRemarkEnabled()) {
auto R = RemarkBuilder();
emit((DiagnosticInfoOptimizationBase &)R);
}

8
llvm/include/llvm/CodeGen/TargetFrameLowering.h
View File

@ -330,12 +330,12 @@ public:
/// Check if given function is safe for not having callee saved registers.
/// This is used when interprocedural register allocation is enabled.
static bool isSafeForNoCSROpt(const Function *F) {
if (!F->hasLocalLinkage() || F->hasAddressTaken() ||
!F->hasFnAttribute(Attribute::NoRecurse))
static bool isSafeForNoCSROpt(const Function &F) {
if (!F.hasLocalLinkage() || F.hasAddressTaken() ||
!F.hasFnAttribute(Attribute::NoRecurse))
return false;
// Function should not be optimized as tail call.
for (const User *U : F->users())
for (const User *U : F.users())
if (auto CS = ImmutableCallSite(U))
if (CS.isTailCall())
return false;

2
llvm/include/llvm/IR/Function.h
View File

@ -131,7 +131,7 @@ public:
// This is here to help easily convert from FunctionT * (Function * or
// MachineFunction *) in BlockFrequencyInfoImpl to Function * by calling
// FunctionT->getFunction().
const Function *getFunction() const { return this; }
const Function &getFunction() const { return *this; }
static Function *Create(FunctionType *Ty, LinkageTypes Linkage,
const Twine &N = "", Module *M = nullptr) {

2
llvm/lib/CodeGen/Analysis.cpp
View File

@ -668,7 +668,7 @@ llvm::getFuncletMembership(const MachineFunction &MF) {
int EntryBBNumber = MF.front().getNumber();
bool IsSEH = isAsynchronousEHPersonality(
classifyEHPersonality(MF.getFunction()->getPersonalityFn()));
classifyEHPersonality(MF.getFunction().getPersonalityFn()));
const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo();
SmallVector<const MachineBasicBlock *, 16> FuncletBlocks;

12
llvm/lib/CodeGen/AsmPrinter/ARMException.cpp
View File

@ -60,16 +60,16 @@ void ARMException::beginFunction(const MachineFunction *MF) {
///
void ARMException::endFunction(const MachineFunction *MF) {
ARMTargetStreamer &ATS = getTargetStreamer();
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
const Function *Per = nullptr;
if (F->hasPersonalityFn())
Per = dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn())
Per = dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
bool forceEmitPersonality =
F->hasPersonalityFn() && !isNoOpWithoutInvoke(classifyEHPersonality(Per)) &&
F->needsUnwindTableEntry();
F.hasPersonalityFn() && !isNoOpWithoutInvoke(classifyEHPersonality(Per)) &&
F.needsUnwindTableEntry();
bool shouldEmitPersonality = forceEmitPersonality ||
!MF->getLandingPads().empty();
if (!Asm->MF->getFunction()->needsUnwindTableEntry() &&
if (!Asm->MF->getFunction().needsUnwindTableEntry() &&
!shouldEmitPersonality)
ATS.emitCantUnwind();
else if (shouldEmitPersonality) {

70
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -621,35 +621,35 @@ void AsmPrinter::EmitDebugThreadLocal(const MCExpr *Value,
/// EmitFunctionHeader - This method emits the header for the current
/// function.
void AsmPrinter::EmitFunctionHeader() {
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
if (isVerbose())
OutStreamer->GetCommentOS()
<< "-- Begin function "
<< GlobalValue::dropLLVMManglingEscape(F->getName()) << '\n';
<< GlobalValue::dropLLVMManglingEscape(F.getName()) << '\n';
// Print out constants referenced by the function
EmitConstantPool();
// Print the 'header' of function.
OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(F, TM));
EmitVisibility(CurrentFnSym, F->getVisibility());
OutStreamer->SwitchSection(getObjFileLowering().SectionForGlobal(&F, TM));
EmitVisibility(CurrentFnSym, F.getVisibility());
EmitLinkage(F, CurrentFnSym);
EmitLinkage(&F, CurrentFnSym);
if (MAI->hasFunctionAlignment())
EmitAlignment(MF->getAlignment(), F);
EmitAlignment(MF->getAlignment(), &F);
if (MAI->hasDotTypeDotSizeDirective())
OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_ELF_TypeFunction);
if (isVerbose()) {
F->printAsOperand(OutStreamer->GetCommentOS(),
/*PrintType=*/false, F->getParent());
F.printAsOperand(OutStreamer->GetCommentOS(),
/*PrintType=*/false, F.getParent());
OutStreamer->GetCommentOS() << '\n';
}
// Emit the prefix data.
if (F->hasPrefixData()) {
if (F.hasPrefixData()) {
if (MAI->hasSubsectionsViaSymbols()) {
// Preserving prefix data on platforms which use subsections-via-symbols
// is a bit tricky. Here we introduce a symbol for the prefix data
@ -658,12 +658,12 @@ void AsmPrinter::EmitFunctionHeader() {
MCSymbol *PrefixSym = OutContext.createLinkerPrivateTempSymbol();
OutStreamer->EmitLabel(PrefixSym);
EmitGlobalConstant(F->getParent()->getDataLayout(), F->getPrefixData());
EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData());
// Emit an .alt_entry directive for the actual function symbol.
OutStreamer->EmitSymbolAttribute(CurrentFnSym, MCSA_AltEntry);
} else {
EmitGlobalConstant(F->getParent()->getDataLayout(), F->getPrefixData());
EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrefixData());
}
}
@ -675,7 +675,7 @@ void AsmPrinter::EmitFunctionHeader() {
// references to the dangling symbols. Emit them at the start of the function
// so that we don't get references to undefined symbols.
std::vector<MCSymbol*> DeadBlockSyms;
MMI->takeDeletedSymbolsForFunction(F, DeadBlockSyms);
MMI->takeDeletedSymbolsForFunction(&F, DeadBlockSyms);
for (unsigned i = 0, e = DeadBlockSyms.size(); i != e; ++i) {
OutStreamer->AddComment("Address taken block that was later removed");
OutStreamer->EmitLabel(DeadBlockSyms[i]);
@ -700,8 +700,8 @@ void AsmPrinter::EmitFunctionHeader() {
}
// Emit the prologue data.
if (F->hasPrologueData())
EmitGlobalConstant(F->getParent()->getDataLayout(), F->getPrologueData());
if (F.hasPrologueData())
EmitGlobalConstant(F.getParent()->getDataLayout(), F.getPrologueData());
}
/// EmitFunctionEntryLabel - Emit the label that is the entrypoint for the
@ -900,7 +900,7 @@ static bool emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) {
AsmPrinter::CFIMoveType AsmPrinter::needsCFIMoves() const {
if (MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI &&
MF->getFunction()->needsUnwindTableEntry())
MF->getFunction().needsUnwindTableEntry())
return CFI_M_EH;
if (MMI->hasDebugInfo())
@ -910,7 +910,7 @@ AsmPrinter::CFIMoveType AsmPrinter::needsCFIMoves() const {
}
bool AsmPrinter::needsSEHMoves() {
return MAI->usesWindowsCFI() && MF->getFunction()->needsUnwindTableEntry();
return MAI->usesWindowsCFI() && MF->getFunction().needsUnwindTableEntry();
}
void AsmPrinter::emitCFIInstruction(const MachineInstr &MI) {
@ -964,7 +964,7 @@ void AsmPrinter::emitStackSizeSection(const MachineFunction &MF) {
OutStreamer->PushSection();
OutStreamer->SwitchSection(StackSizeSection);
const MCSymbol *FunctionSymbol = getSymbol(MF.getFunction());
const MCSymbol *FunctionSymbol = getSymbol(&MF.getFunction());
uint64_t StackSize = FrameInfo.getStackSize();
OutStreamer->EmitValue(MCSymbolRefExpr::create(FunctionSymbol, OutContext),
/* size = */ 8);
@ -980,10 +980,10 @@ static bool needFuncLabelsForEHOrDebugInfo(const MachineFunction &MF,
// We might emit an EH table that uses function begin and end labels even if
// we don't have any landingpads.
if (!MF.getFunction()->hasPersonalityFn())
if (!MF.getFunction().hasPersonalityFn())
return false;
return !isNoOpWithoutInvoke(
classifyEHPersonality(MF.getFunction()->getPersonalityFn()));
classifyEHPersonality(MF.getFunction().getPersonalityFn()));
}
/// EmitFunctionBody - This method emits the body and trailer for a
@ -1070,7 +1070,7 @@ void AsmPrinter::EmitFunctionBody() {
EmittedInsts += NumInstsInFunction;
MachineOptimizationRemarkAnalysis R(DEBUG_TYPE, "InstructionCount",
MF->getFunction()->getSubprogram(),
MF->getFunction().getSubprogram(),
&MF->front());
R << ore::NV("NumInstructions", NumInstsInFunction)
<< " instructions in function";
@ -1098,8 +1098,8 @@ void AsmPrinter::EmitFunctionBody() {
}
}
const Function *F = MF->getFunction();
for (const auto &BB : *F) {
const Function &F = MF->getFunction();
for (const auto &BB : F) {
if (!BB.hasAddressTaken())
continue;
MCSymbol *Sym = GetBlockAddressSymbol(&BB);
@ -1442,7 +1442,7 @@ MCSymbol *AsmPrinter::getCurExceptionSym() {
void AsmPrinter::SetupMachineFunction(MachineFunction &MF) {
this->MF = &MF;
// Get the function symbol.
CurrentFnSym = getSymbol(MF.getFunction());
CurrentFnSym = getSymbol(&MF.getFunction());
CurrentFnSymForSize = CurrentFnSym;
CurrentFnBegin = nullptr;
CurExceptionSym = nullptr;
@ -1568,14 +1568,14 @@ void AsmPrinter::EmitJumpTableInfo() {
// Pick the directive to use to print the jump table entries, and switch to
// the appropriate section.
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
const TargetLoweringObjectFile &TLOF = getObjFileLowering();
bool JTInDiffSection = !TLOF.shouldPutJumpTableInFunctionSection(
MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32,
*F);
F);
if (JTInDiffSection) {
// Drop it in the readonly section.
MCSection *ReadOnlySection = TLOF.getSectionForJumpTable(*F, TM);
MCSection *ReadOnlySection = TLOF.getSectionForJumpTable(F, TM);
OutStreamer->SwitchSection(ReadOnlySection);
}
@ -1949,7 +1949,7 @@ const MCExpr *AsmPrinter::lowerConstant(const Constant *CV) {
raw_string_ostream OS(S);
OS << "Unsupported expression in static initializer: ";
CE->printAsOperand(OS, /*PrintType=*/false,
!MF ? nullptr : MF->getFunction()->getParent());
!MF ? nullptr : MF->getFunction().getParent());
report_fatal_error(OS.str());
}
case Instruction::GetElementPtr: {
@ -2632,7 +2632,7 @@ void AsmPrinter::setupCodePaddingContext(const MachineBasicBlock &MBB,
assert(MF != nullptr && "Machine function must be valid");
assert(LI != nullptr && "Loop info must be valid");
Context.IsPaddingActive = !MF->hasInlineAsm() &&
!MF->getFunction()->optForSize() &&
!MF->getFunction().optForSize() &&
TM.getOptLevel() != CodeGenOpt::None;
const MachineLoop *CurrentLoop = LI->getLoopFor(&MBB);
Context.IsBasicBlockInsideInnermostLoop =
@ -2830,7 +2830,7 @@ void AsmPrinter::emitXRayTable() {
return;
auto PrevSection = OutStreamer->getCurrentSectionOnly();
auto Fn = MF->getFunction();
const Function &F = MF->getFunction();
MCSection *InstMap = nullptr;
MCSection *FnSledIndex = nullptr;
if (MF->getSubtarget().getTargetTriple().isOSBinFormatELF()) {
@ -2838,9 +2838,9 @@ void AsmPrinter::emitXRayTable() {
assert(Associated != nullptr);
auto Flags = ELF::SHF_WRITE | ELF::SHF_ALLOC | ELF::SHF_LINK_ORDER;
std::string GroupName;
if (Fn->hasComdat()) {
if (F.hasComdat()) {
Flags |= ELF::SHF_GROUP;
GroupName = Fn->getComdat()->getName();
GroupName = F.getComdat()->getName();
}
auto UniqueID = ++XRayFnUniqueID;
@ -2886,15 +2886,15 @@ void AsmPrinter::emitXRayTable() {
void AsmPrinter::recordSled(MCSymbol *Sled, const MachineInstr &MI,
SledKind Kind, uint8_t Version) {
auto Fn = MI.getMF()->getFunction();
auto Attr = Fn->getFnAttribute("function-instrument");
bool LogArgs = Fn->hasFnAttribute("xray-log-args");
const Function &F = MI.getMF()->getFunction();
auto Attr = F.getFnAttribute("function-instrument");
bool LogArgs = F.hasFnAttribute("xray-log-args");
bool AlwaysInstrument =
Attr.isStringAttribute() && Attr.getValueAsString() == "xray-always";
if (Kind == SledKind::FUNCTION_ENTER && LogArgs)
Kind = SledKind::LOG_ARGS_ENTER;
Sleds.emplace_back(XRayFunctionEntry{Sled, CurrentFnSym, Kind,
AlwaysInstrument, Fn, Version});
AlwaysInstrument, &F, Version});
}
uint16_t AsmPrinter::getDwarfVersion() const {

2
llvm/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
View File

@ -514,7 +514,7 @@ void AsmPrinter::EmitInlineAsm(const MachineInstr *MI) const {
// Reset SanitizeAddress based on the function's attribute.
MCTargetOptions MCOptions = TM.Options.MCOptions;
MCOptions.SanitizeAddress =
MF->getFunction()->hasFnAttribute(Attribute::SanitizeAddress);
MF->getFunction().hasFnAttribute(Attribute::SanitizeAddress);
EmitInlineAsm(OS.str(), getSubtargetInfo(), MCOptions, LocMD,
MI->getInlineAsmDialect());

16
llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
View File

@ -1154,9 +1154,9 @@ void CodeViewDebug::collectVariableInfo(const DISubprogram *SP) {
}
void CodeViewDebug::beginFunctionImpl(const MachineFunction *MF) {
const Function *GV = MF->getFunction();
assert(FnDebugInfo.count(GV) == false);
CurFn = &FnDebugInfo[GV];
const Function &GV = MF->getFunction();
assert(FnDebugInfo.count(&GV) == false);
CurFn = &FnDebugInfo[&GV];
CurFn->FuncId = NextFuncId++;
CurFn->Begin = Asm->getFunctionBegin();
@ -2273,15 +2273,15 @@ void CodeViewDebug::emitLocalVariable(const LocalVariable &Var) {
}
void CodeViewDebug::endFunctionImpl(const MachineFunction *MF) {
const Function *GV = MF->getFunction();
assert(FnDebugInfo.count(GV));
assert(CurFn == &FnDebugInfo[GV]);
const Function &GV = MF->getFunction();
assert(FnDebugInfo.count(&GV));
assert(CurFn == &FnDebugInfo[&GV]);
collectVariableInfo(GV->getSubprogram());
collectVariableInfo(GV.getSubprogram());
// Don't emit anything if we don't have any line tables.
if (!CurFn->HaveLineInfo) {
FnDebugInfo.erase(GV);
FnDebugInfo.erase(&GV);
CurFn = nullptr;
return;
}

4
llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
View File

@ -179,7 +179,7 @@ static bool hasDebugInfo(const MachineModuleInfo *MMI,
const MachineFunction *MF) {
if (!MMI->hasDebugInfo())
return false;
auto *SP = MF->getFunction()->getSubprogram();
auto *SP = MF->getFunction().getSubprogram();
if (!SP)
return false;
assert(SP->getUnit());
@ -223,7 +223,7 @@ void DebugHandlerBase::beginFunction(const MachineFunction *MF) {
// label, so arguments are visible when breaking at function entry.
const DILocalVariable *DIVar = Ranges.front().first->getDebugVariable();
if (DIVar->isParameter() &&
getDISubprogram(DIVar->getScope())->describes(MF->getFunction())) {
getDISubprogram(DIVar->getScope())->describes(&MF->getFunction())) {
LabelsBeforeInsn[Ranges.front().first] = Asm->getFunctionBegin();
if (Ranges.front().first->getDebugExpression()->isFragment()) {
// Mark all non-overlapping initial fragments.

14
llvm/lib/CodeGen/AsmPrinter/DwarfCFIException.cpp
View File

@ -87,7 +87,7 @@ static MCSymbol *getExceptionSym(AsmPrinter *Asm) {
void DwarfCFIException::beginFunction(const MachineFunction *MF) {
shouldEmitMoves = shouldEmitPersonality = shouldEmitLSDA = false;
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
// If any landing pads survive, we need an EH table.
bool hasLandingPads = !MF->getLandingPads().empty();
@ -100,17 +100,17 @@ void DwarfCFIException::beginFunction(const MachineFunction *MF) {
const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering();
unsigned PerEncoding = TLOF.getPersonalityEncoding();
const Function *Per = nullptr;
if (F->hasPersonalityFn())
Per = dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn())
Per = dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
// Emit a personality function even when there are no landing pads
forceEmitPersonality =
// ...if a personality function is explicitly specified
F->hasPersonalityFn() &&
F.hasPersonalityFn() &&
// ... and it's not known to be a noop in the absence of invokes
!isNoOpWithoutInvoke(classifyEHPersonality(Per)) &&
// ... and we're not explicitly asked not to emit it
F->needsUnwindTableEntry();
F.needsUnwindTableEntry();
shouldEmitPersonality =
(forceEmitPersonality ||
@ -143,8 +143,8 @@ void DwarfCFIException::beginFragment(const MachineBasicBlock *MBB,
if (!shouldEmitPersonality)
return;
auto *F = MBB->getParent()->getFunction();
auto *P = dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
auto &F = MBB->getParent()->getFunction();
auto *P = dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
assert(P && "Expected personality function");
// If we are forced to emit this personality, make sure to record

6
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
View File

@ -1163,7 +1163,7 @@ void DwarfDebug::beginInstruction(const MachineInstr *MI) {
DebugHandlerBase::beginInstruction(MI);
assert(CurMI);
const auto *SP = MI->getMF()->getFunction()->getSubprogram();
const auto *SP = MI->getMF()->getFunction().getSubprogram();
if (!SP || SP->getUnit()->getEmissionKind() == DICompileUnit::NoDebug)
return;
@ -1261,7 +1261,7 @@ static DebugLoc findPrologueEndLoc(const MachineFunction *MF) {
void DwarfDebug::beginFunctionImpl(const MachineFunction *MF) {
CurFn = MF;
auto *SP = MF->getFunction()->getSubprogram();
auto *SP = MF->getFunction().getSubprogram();
assert(LScopes.empty() || SP == LScopes.getCurrentFunctionScope()->getScopeNode());
if (SP->getUnit()->getEmissionKind() == DICompileUnit::NoDebug)
return;
@ -1297,7 +1297,7 @@ void DwarfDebug::skippedNonDebugFunction() {
// Gather and emit post-function debug information.
void DwarfDebug::endFunctionImpl(const MachineFunction *MF) {
const DISubprogram *SP = MF->getFunction()->getSubprogram();
const DISubprogram *SP = MF->getFunction().getSubprogram();
assert(CurFn == MF &&
"endFunction should be called with the same function as beginFunction");

50
llvm/lib/CodeGen/AsmPrinter/WinException.cpp
View File

@ -63,7 +63,7 @@ void WinException::beginFunction(const MachineFunction *MF) {
bool hasLandingPads = !MF->getLandingPads().empty();
bool hasEHFunclets = MF->hasEHFunclets();
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
shouldEmitMoves = Asm->needsSEHMoves() && MF->hasWinCFI();
@ -72,14 +72,14 @@ void WinException::beginFunction(const MachineFunction *MF) {
EHPersonality Per = EHPersonality::Unknown;
const Function *PerFn = nullptr;
if (F->hasPersonalityFn()) {
PerFn = dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn()) {
PerFn = dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
Per = classifyEHPersonality(PerFn);
}
bool forceEmitPersonality = F->hasPersonalityFn() &&
bool forceEmitPersonality = F.hasPersonalityFn() &&
!isNoOpWithoutInvoke(Per) &&
F->needsUnwindTableEntry();
F.needsUnwindTableEntry();
shouldEmitPersonality =
forceEmitPersonality || ((hasLandingPads || hasEHFunclets) &&
@ -98,7 +98,7 @@ void WinException::beginFunction(const MachineFunction *MF) {
// functions may still refer to it.
const WinEHFuncInfo &FuncInfo = *MF->getWinEHFuncInfo();
StringRef FLinkageName =
GlobalValue::dropLLVMManglingEscape(MF->getFunction()->getName());
GlobalValue::dropLLVMManglingEscape(MF->getFunction().getName());
emitEHRegistrationOffsetLabel(FuncInfo, FLinkageName);
}
shouldEmitLSDA = hasEHFunclets;
@ -115,10 +115,10 @@ void WinException::endFunction(const MachineFunction *MF) {
if (!shouldEmitPersonality && !shouldEmitMoves && !shouldEmitLSDA)
return;
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
EHPersonality Per = EHPersonality::Unknown;
if (F->hasPersonalityFn())
Per = classifyEHPersonality(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn())
Per = classifyEHPersonality(F.getPersonalityFn()->stripPointerCasts());
// Get rid of any dead landing pads if we're not using funclets. In funclet
// schemes, the landing pad is not actually reachable. It only exists so
@ -170,8 +170,8 @@ static MCSymbol *getMCSymbolForMBB(AsmPrinter *Asm,
// Give catches and cleanups a name based off of their parent function and
// their funclet entry block's number.
const MachineFunction *MF = MBB->getParent();
const Function *F = MF->getFunction();
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F->getName());
const Function &F = MF->getFunction();
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F.getName());
MCContext &Ctx = MF->getContext();
StringRef HandlerPrefix = MBB->isCleanupFuncletEntry() ? "dtor" : "catch";
return Ctx.getOrCreateSymbol("?" + HandlerPrefix + "$" +
@ -183,7 +183,7 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB,
MCSymbol *Sym) {
CurrentFuncletEntry = &MBB;
const Function *F = Asm->MF->getFunction();
const Function &F = Asm->MF->getFunction();
// If a symbol was not provided for the funclet, invent one.
if (!Sym) {
Sym = getMCSymbolForMBB(Asm, &MBB);
@ -198,7 +198,7 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB,
// We want our funclet's entry point to be aligned such that no nops will be
// present after the label.
Asm->EmitAlignment(std::max(Asm->MF->getAlignment(), MBB.getAlignment()),
F);
&F);
// Now that we've emitted the alignment directive, point at our funclet.
Asm->OutStreamer->EmitLabel(Sym);
@ -215,8 +215,8 @@ void WinException::beginFunclet(const MachineBasicBlock &MBB,
const Function *PerFn = nullptr;
// Determine which personality routine we are using for this funclet.
if (F->hasPersonalityFn())
PerFn = dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn())
PerFn = dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
const MCSymbol *PersHandlerSym =
TLOF.getCFIPersonalitySymbol(PerFn, Asm->TM, MMI);
@ -237,10 +237,10 @@ void WinException::endFunclet() {
const MachineFunction *MF = Asm->MF;
if (shouldEmitMoves || shouldEmitPersonality) {
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
EHPersonality Per = EHPersonality::Unknown;
if (F->hasPersonalityFn())
Per = classifyEHPersonality(F->getPersonalityFn()->stripPointerCasts());
if (F.hasPersonalityFn())
Per = classifyEHPersonality(F.getPersonalityFn()->stripPointerCasts());
// Emit an UNWIND_INFO struct describing the prologue.
Asm->OutStreamer->EmitWinEHHandlerData();
@ -249,7 +249,7 @@ void WinException::endFunclet() {
!CurrentFuncletEntry->isCleanupFuncletEntry()) {
// If this is a C++ catch funclet (or the parent function),
// emit a reference to the LSDA for the parent function.
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F->getName());
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F.getName());
MCSymbol *FuncInfoXData = Asm->OutContext.getOrCreateSymbol(
Twine("$cppxdata$", FuncLinkageName));
Asm->OutStreamer->EmitValue(create32bitRef(FuncInfoXData), 4);
@ -533,7 +533,7 @@ void WinException::emitCSpecificHandlerTable(const MachineFunction *MF) {
// Emit a label assignment with the SEH frame offset so we can use it for
// llvm.x86.seh.recoverfp.
StringRef FLinkageName =
GlobalValue::dropLLVMManglingEscape(MF->getFunction()->getName());
GlobalValue::dropLLVMManglingEscape(MF->getFunction().getName());
MCSymbol *ParentFrameOffset =
Ctx.getOrCreateParentFrameOffsetSymbol(FLinkageName);
const MCExpr *MCOffset =
@ -628,11 +628,11 @@ void WinException::emitSEHActionsForRange(const WinEHFuncInfo &FuncInfo,
}
void WinException::emitCXXFrameHandler3Table(const MachineFunction *MF) {
const Function *F = MF->getFunction();
const Function &F = MF->getFunction();
auto &OS = *Asm->OutStreamer;
const WinEHFuncInfo &FuncInfo = *MF->getWinEHFuncInfo();
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F->getName());
StringRef FuncLinkageName = GlobalValue::dropLLVMManglingEscape(F.getName());
SmallVector<std::pair<const MCExpr *, int>, 4> IPToStateTable;
MCSymbol *FuncInfoXData = nullptr;
@ -938,8 +938,8 @@ void WinException::emitEHRegistrationOffsetLabel(const WinEHFuncInfo &FuncInfo,
/// indexed by state number instead of IP.
void WinException::emitExceptHandlerTable(const MachineFunction *MF) {
MCStreamer &OS = *Asm->OutStreamer;
const Function *F = MF->getFunction();
StringRef FLinkageName = GlobalValue::dropLLVMManglingEscape(F->getName());
const Function &F = MF->getFunction();
StringRef FLinkageName = GlobalValue::dropLLVMManglingEscape(F.getName());
bool VerboseAsm = OS.isVerboseAsm();
auto AddComment = [&](const Twine &Comment) {
@ -956,7 +956,7 @@ void WinException::emitExceptHandlerTable(const MachineFunction *MF) {
OS.EmitLabel(LSDALabel);
const Function *Per =
dyn_cast<Function>(F->getPersonalityFn()->stripPointerCasts());
dyn_cast<Function>(F.getPersonalityFn()->stripPointerCasts());
StringRef PerName = Per->getName();
int BaseState = -1;
if (PerName == "_except_handler4") {

6
llvm/lib/CodeGen/BranchFolding.cpp
View File

@ -118,7 +118,7 @@ INITIALIZE_PASS(BranchFolderPass, DEBUG_TYPE,
"Control Flow Optimizer", false, false)
bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
@ -685,7 +685,7 @@ ProfitableToMerge(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2,
// branch instruction, which is likely to be smaller than the 2
// instructions that would be deleted in the merge.
MachineFunction *MF = MBB1->getParent();
return EffectiveTailLen >= 2 && MF->getFunction()->optForSize() &&
return EffectiveTailLen >= 2 && MF->getFunction().optForSize() &&
(I1 == MBB1->begin() || I2 == MBB2->begin());
}
@ -1511,7 +1511,7 @@ ReoptimizeBlock:
}
if (!IsEmptyBlock(MBB) && MBB->pred_size() == 1 &&
MF.getFunction()->optForSize()) {
MF.getFunction().optForSize()) {
// Changing "Jcc foo; foo: jmp bar;" into "Jcc bar;" might change the branch
// direction, thereby defeating careful block placement and regressing
// performance. Therefore, only consider this for optsize functions.

2
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
View File

@ -94,7 +94,7 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
}
bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
bool AnyChanges = false;

2
llvm/lib/CodeGen/EarlyIfConversion.cpp
View File

@ -785,7 +785,7 @@ bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
<< "********** Function: " << MF.getName() << '\n');
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
// Only run if conversion if the target wants it.

2
llvm/lib/CodeGen/ExecutionDepsFix.cpp
View File

@ -617,7 +617,7 @@ bool ExecutionDepsFix::isBlockDone(MachineBasicBlock *MBB) {
}
bool ExecutionDepsFix::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(*mf.getFunction()))
if (skipFunction(mf.getFunction()))
return false;
MF = &mf;
TII = MF->getSubtarget().getInstrInfo();

2
llvm/lib/CodeGen/FEntryInserter.cpp
View File

@ -36,7 +36,7 @@ struct FEntryInserter : public MachineFunctionPass {
bool FEntryInserter::runOnMachineFunction(MachineFunction &MF) {
const std::string FEntryName =
MF.getFunction()->getFnAttribute("fentry-call").getValueAsString();
MF.getFunction().getFnAttribute("fentry-call").getValueAsString();
if (FEntryName != "true")
return false;

4
llvm/lib/CodeGen/GCRootLowering.cpp
View File

@ -328,10 +328,10 @@ void GCMachineCodeAnalysis::FindStackOffsets(MachineFunction &MF) {
bool GCMachineCodeAnalysis::runOnMachineFunction(MachineFunction &MF) {
// Quick exit for functions that do not use GC.
if (!MF.getFunction()->hasGC())
if (!MF.getFunction().hasGC())
return false;
FI = &getAnalysis<GCModuleInfo>().getFunctionInfo(*MF.getFunction());
FI = &getAnalysis<GCModuleInfo>().getFunctionInfo(MF.getFunction());
MMI = &getAnalysis<MachineModuleInfo>();
TII = MF.getSubtarget().getInstrInfo();

2
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
View File

@ -108,7 +108,7 @@ bool CallLowering::handleAssignments(MachineIRBuilder &MIRBuilder,
ArrayRef<ArgInfo> Args,
ValueHandler &Handler) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
SmallVector<CCValAssign, 16> ArgLocs;

16
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -124,8 +124,8 @@ unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
bool Success = translate(*CV, VReg);
if (!Success) {
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
MF->getFunction()->getSubprogram(),
&MF->getFunction()->getEntryBlock());
MF->getFunction().getSubprogram(),
&MF->getFunction().getEntryBlock());
R << "unable to translate constant: " << ore::NV("Type", Val.getType());
reportTranslationError(*MF, *TPC, *ORE, R);
return VReg;
@ -591,7 +591,7 @@ void IRTranslator::getStackGuard(unsigned DstReg,
MIB.addDef(DstReg);
auto &TLI = *MF->getSubtarget().getTargetLowering();
Value *Global = TLI.getSDagStackGuard(*MF->getFunction()->getParent());
Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
if (!Global)
return;
@ -925,7 +925,7 @@ bool IRTranslator::translateLandingPad(const User &U,
// If there aren't registers to copy the values into (e.g., during SjLj
// exceptions), then don't bother.
auto &TLI = *MF->getSubtarget().getTargetLowering();
const Constant *PersonalityFn = MF->getFunction()->getPersonalityFn();
const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
return true;
@ -1236,7 +1236,7 @@ void IRTranslator::finalizeFunction() {
bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
MF = &CurMF;
const Function &F = *MF->getFunction();
const Function &F = MF->getFunction();
if (F.empty())
return false;
CLI = MF->getSubtarget().getCallLowering();
@ -1252,8 +1252,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
if (!DL->isLittleEndian()) {
// Currently we don't properly handle big endian code.
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
MF->getFunction()->getSubprogram(),
&MF->getFunction()->getEntryBlock());
F.getSubprogram(), &F.getEntryBlock());
R << "unable to translate in big endian mode";
reportTranslationError(*MF, *TPC, *ORE, R);
}
@ -1289,8 +1288,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
}
if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
MF->getFunction()->getSubprogram(),
&MF->getFunction()->getEntryBlock());
F.getSubprogram(), &F.getEntryBlock());
R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
reportTranslationError(*MF, *TPC, *ORE, R);
return false;

2
llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
View File

@ -189,7 +189,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
if (MF.size() != NumBlocks) {
MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
MF.getFunction()->getSubprogram(),
MF.getFunction().getSubprogram(),
/*MBB=*/nullptr);
R << "inserting blocks is not supported yet";
reportGISelFailure(MF, TPC, MORE, R);

2
llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
View File

@ -175,7 +175,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
// outerloop for that.
if (MF.size() != NumBlocks) {
MachineOptimizationRemarkMissed R("gisel-legalize", "GISelFailure",
MF.getFunction()->getSubprogram(),
MF.getFunction().getSubprogram(),
/*MBB=*/nullptr);
R << "inserting blocks is not supported yet";
reportGISelFailure(MF, TPC, MORE, R);

6
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -136,7 +136,7 @@ LegalizerHelper::LegalizeResult
LegalizerHelper::libcall(MachineInstr &MI) {
LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
unsigned Size = LLTy.getSizeInBits();
auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
MIRBuilder.setInstr(MI);
@ -410,7 +410,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
return UnableToLegalize;
int NumParts = SizeOp0 / NarrowSize;
const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
SmallVector<unsigned, 2> DstRegs;
for (int i = 0; i < NumParts; ++i) {
@ -824,7 +824,7 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
return UnableToLegalize;
unsigned Res = MI.getOperand(0).getReg();
Type *ZeroTy;
LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
switch (Ty.getSizeInBits()) {
case 16:
ZeroTy = Type::getHalfTy(Ctx);

4
llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
View File

@ -263,7 +263,7 @@ MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
const ConstantInt *NewVal = &Val;
if (Ty.getSizeInBits() != Val.getBitWidth())
NewVal = ConstantInt::get(MF->getFunction()->getContext(),
NewVal = ConstantInt::get(MF->getFunction().getContext(),
Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
@ -271,7 +271,7 @@ MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
int64_t Val) {
auto IntN = IntegerType::get(MF->getFunction()->getContext(),
auto IntN = IntegerType::get(MF->getFunction().getContext(),
MRI->getType(Res).getSizeInBits());
ConstantInt *CI = ConstantInt::get(IntN, Val, true);
return buildConstant(Res, *CI);

4
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
View File

@ -601,9 +601,9 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
return false;
DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
const Function *F = MF.getFunction();
const Function &F = MF.getFunction();
Mode SaveOptMode = OptMode;
if (F->hasFnAttribute(Attribute::OptimizeNone))
if (F.hasFnAttribute(Attribute::OptimizeNone))
OptMode = Mode::Fast;
init(MF);

2
llvm/lib/CodeGen/IfConversion.cpp
View File

@ -337,7 +337,7 @@ INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
INITIALIZE_PASS_END(IfConverter, DEBUG_TYPE, "If Converter", false, false)
bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()) || (PredicateFtor && !PredicateFtor(MF)))
if (skipFunction(MF.getFunction()) || (PredicateFtor && !PredicateFtor(MF)))
return false;
const TargetSubtargetInfo &ST = MF.getSubtarget();

4
llvm/lib/CodeGen/LexicalScopes.cpp
View File

@ -49,7 +49,7 @@ void LexicalScopes::reset() {
void LexicalScopes::initialize(const MachineFunction &Fn) {
reset();
// Don't attempt any lexical scope creation for a NoDebug compile unit.
if (Fn.getFunction()->getSubprogram()->getUnit()->getEmissionKind() ==
if (Fn.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
DICompileUnit::NoDebug)
return;
MF = &Fn;
@ -173,7 +173,7 @@ LexicalScopes::getOrCreateRegularScope(const DILocalScope *Scope) {
false)).first;
if (!Parent) {
assert(cast<DISubprogram>(Scope)->describes(MF->getFunction()));
assert(cast<DISubprogram>(Scope)->describes(&MF->getFunction()));
assert(!CurrentFnLexicalScope);
CurrentFnLexicalScope = &I->second;
}

4
llvm/lib/CodeGen/LiveDebugValues.cpp
View File

@ -703,12 +703,12 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
}
bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
if (!MF.getFunction()->getSubprogram())
if (!MF.getFunction().getSubprogram())
// LiveDebugValues will already have removed all DBG_VALUEs.
return false;
// Skip functions from NoDebug compilation units.
if (MF.getFunction()->getSubprogram()->getUnit()->getEmissionKind() ==
if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
DICompileUnit::NoDebug)
return false;

2
llvm/lib/CodeGen/LiveDebugVariables.cpp
View File

@ -833,7 +833,7 @@ static void removeDebugValues(MachineFunction &mf) {
bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
if (!EnableLDV)
return false;
if (!mf.getFunction()->getSubprogram()) {
if (!mf.getFunction().getSubprogram()) {
removeDebugValues(mf);
return false;
}

2
llvm/lib/CodeGen/LiveRangeShrink.cpp
View File

@ -106,7 +106,7 @@ static void BuildInstOrderMap(MachineBasicBlock::iterator Start,
}
bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
MachineRegisterInfo &MRI = MF.getRegInfo();

22
llvm/lib/CodeGen/MIRParser/MIParser.cpp
View File

@ -431,7 +431,7 @@ bool MIParser::parseBasicBlockDefinition(
break;
case MIToken::IRBlock:
// TODO: Report an error when both name and ir block are specified.
if (parseIRBlock(BB, *MF.getFunction()))
if (parseIRBlock(BB, MF.getFunction()))
return true;
lex();
break;
@ -447,7 +447,7 @@ bool MIParser::parseBasicBlockDefinition(
if (!Name.empty()) {
BB = dyn_cast_or_null<BasicBlock>(
MF.getFunction()->getValueSymbolTable()->lookup(Name));
MF.getFunction().getValueSymbolTable()->lookup(Name));
if (!BB)
return error(Loc, Twine("basic block '") + Name +
"' is not defined in the function '" +
@ -1234,7 +1234,7 @@ bool MIParser::parseIRConstant(StringRef::iterator Loc, StringRef StringValue,
const Constant *&C) {
auto Source = StringValue.str(); // The source has to be null terminated.
SMDiagnostic Err;
C = parseConstantValue(Source, Err, *MF.getFunction()->getParent(),
C = parseConstantValue(Source, Err, *MF.getFunction().getParent(),
&PFS.IRSlots);
if (!C)
return error(Loc + Err.getColumnNo(), Err.getMessage());
@ -1254,7 +1254,7 @@ bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
lex();
return false;
} else if (Token.is(MIToken::PointerType)) {
const DataLayout &DL = MF.getFunction()->getParent()->getDataLayout();
const DataLayout &DL = MF.getDataLayout();
unsigned AS = APSInt(Token.range().drop_front()).getZExtValue();
Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
lex();
@ -1419,7 +1419,7 @@ bool MIParser::parseFixedStackObjectOperand(MachineOperand &Dest) {
bool MIParser::parseGlobalValue(GlobalValue *&GV) {
switch (Token.kind()) {
case MIToken::NamedGlobalValue: {
const Module *M = MF.getFunction()->getParent();
const Module *M = MF.getFunction().getParent();
GV = M->getNamedValue(Token.stringValue());
if (!GV)
return error(Twine("use of undefined global value '") + Token.range() +
@ -1557,7 +1557,7 @@ bool MIParser::parseDIExpression(MDNode *&Expr) {
if (expectAndConsume(MIToken::rparen))
return true;
Expr = DIExpression::get(MF.getFunction()->getContext(), Elements);
Expr = DIExpression::get(MF.getFunction().getContext(), Elements);
return false;
}
@ -2102,7 +2102,7 @@ bool MIParser::parseOperandsOffset(MachineOperand &Op) {
bool MIParser::parseIRValue(const Value *&V) {
switch (Token.kind()) {
case MIToken::NamedIRValue: {
V = MF.getFunction()->getValueSymbolTable()->lookup(Token.stringValue());
V = MF.getFunction().getValueSymbolTable()->lookup(Token.stringValue());
break;
}
case MIToken::IRValue: {
@ -2361,7 +2361,7 @@ bool MIParser::parseMachineMemoryOperand(MachineMemOperand *&Dest) {
// Optional synchronization scope.
SyncScope::ID SSID;
if (parseOptionalScope(MF.getFunction()->getContext(), SSID))
if (parseOptionalScope(MF.getFunction().getContext(), SSID))
return true;
// Up to two atomic orderings (cmpxchg provides guarantees on failure).
@ -2542,12 +2542,12 @@ static const BasicBlock *getIRBlockFromSlot(
const BasicBlock *MIParser::getIRBlock(unsigned Slot) {
if (Slots2BasicBlocks.empty())
initSlots2BasicBlocks(*MF.getFunction(), Slots2BasicBlocks);
initSlots2BasicBlocks(MF.getFunction(), Slots2BasicBlocks);
return getIRBlockFromSlot(Slot, Slots2BasicBlocks);
}
const BasicBlock *MIParser::getIRBlock(unsigned Slot, const Function &F) {
if (&F == MF.getFunction())
if (&F == &MF.getFunction())
return getIRBlock(Slot);
DenseMap<unsigned, const BasicBlock *> CustomSlots2BasicBlocks;
initSlots2BasicBlocks(F, CustomSlots2BasicBlocks);
@ -2578,7 +2578,7 @@ static void initSlots2Values(const Function &F,
const Value *MIParser::getIRValue(unsigned Slot) {
if (Slots2Values.empty())
initSlots2Values(*MF.getFunction(), Slots2Values);
initSlots2Values(MF.getFunction(), Slots2Values);
auto ValueInfo = Slots2Values.find(Slot);
if (ValueInfo == Slots2Values.end())
return nullptr;

4
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
View File

@ -551,7 +551,7 @@ bool MIRParserImpl::initializeFrameInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
MachineFrameInfo &MFI = MF.getFrameInfo();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
const yaml::MachineFrameInfo &YamlMFI = YamlMF.FrameInfo;
MFI.setFrameAddressIsTaken(YamlMFI.IsFrameAddressTaken);
MFI.setReturnAddressIsTaken(YamlMFI.IsReturnAddressTaken);
@ -722,7 +722,7 @@ bool MIRParserImpl::initializeConstantPool(PerFunctionMIParsingState &PFS,
MachineConstantPool &ConstantPool, const yaml::MachineFunction &YamlMF) {
DenseMap<unsigned, unsigned> &ConstantPoolSlots = PFS.ConstantPoolSlots;
const MachineFunction &MF = PFS.MF;
const auto &M = *MF.getFunction()->getParent();
const auto &M = *MF.getFunction().getParent();
SMDiagnostic Error;
for (const auto &YamlConstant : YamlMF.Constants) {
if (YamlConstant.IsTargetSpecific)

6
llvm/lib/CodeGen/MIRPrinter.cpp
View File

@ -213,8 +213,8 @@ void MIRPrinter::print(const MachineFunction &MF) {
MachineFunctionProperties::Property::Selected);
convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
ModuleSlotTracker MST(MF.getFunction()->getParent());
MST.incorporateFunction(*MF.getFunction());
ModuleSlotTracker MST(MF.getFunction().getParent());
MST.incorporateFunction(MF.getFunction());
convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
convertStackObjects(YamlMF, MF, MST);
if (const auto *ConstantPool = MF.getConstantPool())
@ -696,7 +696,7 @@ void MIPrinter::print(const MachineInstr &MI) {
if (!MI.memoperands_empty()) {
OS << " :: ";
const LLVMContext &Context = MF->getFunction()->getContext();
const LLVMContext &Context = MF->getFunction().getContext();
bool NeedComma = false;
for (const auto *Op : MI.memoperands()) {
if (NeedComma)

4
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -267,8 +267,8 @@ void MachineBasicBlock::print(raw_ostream &OS, const SlotIndexes *Indexes)
<< " is null\n";
return;
}
const Function *F = MF->getFunction();
const Module *M = F ? F->getParent() : nullptr;
const Function &F = MF->getFunction();
const Module *M = F.getParent();
ModuleSlotTracker MST(M);
print(OS, MST, Indexes);
}

8
llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp
View File

@ -224,14 +224,14 @@ MachineBlockFrequencyInfo::getBlockFreq(const MachineBasicBlock *MBB) const {
Optional<uint64_t> MachineBlockFrequencyInfo::getBlockProfileCount(
const MachineBasicBlock *MBB) const {
const Function *F = MBFI->getFunction()->getFunction();
return MBFI ? MBFI->getBlockProfileCount(*F, MBB) : None;
const Function &F = MBFI->getFunction()->getFunction();
return MBFI ? MBFI->getBlockProfileCount(F, MBB) : None;
}
Optional<uint64_t>
MachineBlockFrequencyInfo::getProfileCountFromFreq(uint64_t Freq) const {
const Function *F = MBFI->getFunction()->getFunction();
return MBFI ? MBFI->getProfileCountFromFreq(*F, Freq) : None;
const Function &F = MBFI->getFunction()->getFunction();
return MBFI ? MBFI->getProfileCountFromFreq(F, Freq) : None;
}
bool

16
llvm/lib/CodeGen/MachineBlockPlacement.cpp
View File

@ -1235,7 +1235,7 @@ void MachineBlockPlacement::precomputeTriangleChains() {
// When profile is available, we need to handle the triangle-shape CFG.
static BranchProbability getLayoutSuccessorProbThreshold(
const MachineBasicBlock *BB) {
if (!BB->getParent()->getFunction()->getEntryCount())
if (!BB->getParent()->getFunction().getEntryCount())
return BranchProbability(StaticLikelyProb, 100);
if (BB->succ_size() == 2) {
const MachineBasicBlock *Succ1 = *BB->succ_begin();
@ -1769,7 +1769,7 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L,
// i.e. when the layout predecessor does not fallthrough to the loop header.
// In practice this never happens though: there always seems to be a preheader
// that can fallthrough and that is also placed before the header.
if (F->getFunction()->optForSize())
if (F->getFunction().optForSize())
return L.getHeader();
// Check that the header hasn't been fused with a preheader block due to
@ -2178,7 +2178,7 @@ MachineBlockPlacement::collectLoopBlockSet(const MachineLoop &L) {
// will be merged into the first outer loop chain for which this block is not
// cold anymore. This needs precise profile data and we only do this when
// profile data is available.
if (F->getFunction()->getEntryCount() || ForceLoopColdBlock) {
if (F->getFunction().getEntryCount() || ForceLoopColdBlock) {
BlockFrequency LoopFreq(0);
for (auto LoopPred : L.getHeader()->predecessors())
if (!L.contains(LoopPred))
@ -2220,7 +2220,7 @@ void MachineBlockPlacement::buildLoopChains(const MachineLoop &L) {
// for better layout.
bool RotateLoopWithProfile =
ForcePreciseRotationCost ||
(PreciseRotationCost && F->getFunction()->getEntryCount());
(PreciseRotationCost && F->getFunction().getEntryCount());
// First check to see if there is an obviously preferable top block for the
// loop. This will default to the header, but may end up as one of the
@ -2485,7 +2485,7 @@ void MachineBlockPlacement::alignBlocks() {
// exclusively on the loop info here so that we can align backedges in
// unnatural CFGs and backedges that were introduced purely because of the
// loop rotations done during this layout pass.
if (F->getFunction()->optForSize())
if (F->getFunction().optForSize())
return;
BlockChain &FunctionChain = *BlockToChain[&F->front()];
if (FunctionChain.begin() == FunctionChain.end())
@ -2715,7 +2715,7 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock(
}
bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
// Check for single-block functions and skip them.
@ -2760,7 +2760,7 @@ bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
if (TailDupPlacement) {
MPDT = &getAnalysis<MachinePostDominatorTree>();
if (MF.getFunction()->optForSize())
if (MF.getFunction().optForSize())
TailDupSize = 1;
bool PreRegAlloc = false;
TailDup.initMF(MF, PreRegAlloc, MBPI, /* LayoutMode */ true, TailDupSize);
@ -2817,7 +2817,7 @@ bool MachineBlockPlacement::runOnMachineFunction(MachineFunction &MF) {
}
if (ViewBlockLayoutWithBFI != GVDT_None &&
(ViewBlockFreqFuncName.empty() ||
F->getFunction()->getName().equals(ViewBlockFreqFuncName))) {
F->getFunction().getName().equals(ViewBlockFreqFuncName))) {
MBFI->view("MBP." + MF.getName(), false);
}

2
llvm/lib/CodeGen/MachineCSE.cpp
View File

@ -727,7 +727,7 @@ bool MachineCSE::PerformCSE(MachineDomTreeNode *Node) {
}
bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TII = MF.getSubtarget().getInstrInfo();

2
llvm/lib/CodeGen/MachineCombiner.cpp
View File

@ -548,7 +548,7 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
MLI = &getAnalysis<MachineLoopInfo>();
Traces = &getAnalysis<MachineTraceMetrics>();
MinInstr = nullptr;
OptSize = MF.getFunction()->optForSize();
OptSize = MF.getFunction().optForSize();
DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
if (!TII->useMachineCombiner()) {

2
llvm/lib/CodeGen/MachineCopyPropagation.cpp
View File

@ -378,7 +378,7 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
}
bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
Changed = false;

9
llvm/lib/CodeGen/MachineFunction.cpp
View File

@ -244,7 +244,7 @@ getOrCreateJumpTableInfo(unsigned EntryKind) {
/// Should we be emitting segmented stack stuff for the function
bool MachineFunction::shouldSplitStack() const {
return getFunction()->hasFnAttribute("split-stack");
return getFunction().hasFnAttribute("split-stack");
}
/// This discards all of the MachineBasicBlock numbers and recomputes them.
@ -485,8 +485,7 @@ LLVM_DUMP_METHOD void MachineFunction::dump() const {
#endif
StringRef MachineFunction::getName() const {
assert(getFunction() && "No function!");
return getFunction()->getName();
return getFunction().getName();
}
void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
@ -519,8 +518,8 @@ void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const {
OS << '\n';
}
ModuleSlotTracker MST(getFunction()->getParent());
MST.incorporateFunction(*getFunction());
ModuleSlotTracker MST(getFunction().getParent());
MST.incorporateFunction(getFunction());
for (const auto &BB : *this) {
OS << '\n';
BB.print(OS, MST, Indexes);

2
llvm/lib/CodeGen/MachineInstr.cpp
View File

@ -1211,7 +1211,7 @@ void MachineInstr::print(raw_ostream &OS, bool SkipOpers, bool SkipDebugLoc,
const Module *M = nullptr;
if (const MachineBasicBlock *MBB = getParent())
if (const MachineFunction *MF = MBB->getParent())
M = MF->getFunction()->getParent();
M = MF->getFunction().getParent();
ModuleSlotTracker MST(M);
print(OS, MST, SkipOpers, SkipDebugLoc, TII);

2
llvm/lib/CodeGen/MachineLICM.cpp
View File

@ -280,7 +280,7 @@ static bool LoopIsOuterMostWithPredecessor(MachineLoop *CurLoop) {
}
bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
Changed = FirstInLoop = false;

4
llvm/lib/CodeGen/MachineOptimizationRemarkEmitter.cpp
View File

@ -50,7 +50,7 @@ void MachineOptimizationRemarkEmitter::emit(
auto &OptDiag = cast<DiagnosticInfoMIROptimization>(OptDiagCommon);
computeHotness(OptDiag);
LLVMContext &Ctx = MF.getFunction()->getContext();
LLVMContext &Ctx = MF.getFunction().getContext();
// Only emit it if its hotness meets the threshold.
if (OptDiag.getHotness().getValueOr(0) <
@ -71,7 +71,7 @@ bool MachineOptimizationRemarkEmitterPass::runOnMachineFunction(
MachineFunction &MF) {
MachineBlockFrequencyInfo *MBFI;
if (MF.getFunction()->getContext().getDiagnosticsHotnessRequested())
if (MF.getFunction().getContext().getDiagnosticsHotnessRequested())
MBFI = &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI();
else
MBFI = nullptr;

4
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -729,13 +729,13 @@ INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
/// The "main" function for implementing Swing Modulo Scheduling.
bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(*mf.getFunction()))
if (skipFunction(mf.getFunction()))
return false;
if (!EnableSWP)
return false;
if (mf.getFunction()->getAttributes().hasAttribute(
if (mf.getFunction().getAttributes().hasAttribute(
AttributeList::FunctionIndex, Attribute::OptimizeForSize) &&
!EnableSWPOptSize.getPosition())
return false;

2
llvm/lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -531,7 +531,7 @@ static bool isNoReturnDef(const MachineOperand &MO) {
const MachineFunction &MF = *MBB.getParent();
// We need to keep correct unwind information even if the function will
// not return, since the runtime may need it.
if (MF.getFunction()->hasFnAttribute(Attribute::UWTable))
if (MF.getFunction().hasFnAttribute(Attribute::UWTable))
return false;
const Function *Called = getCalledFunction(MI);
return !(Called == nullptr || !Called->hasFnAttribute(Attribute::NoReturn) ||

4
llvm/lib/CodeGen/MachineScheduler.cpp
View File

@ -351,7 +351,7 @@ ScheduleDAGInstrs *PostMachineScheduler::createPostMachineScheduler() {
/// design would be to split blocks at scheduling boundaries, but LLVM has a
/// general bias against block splitting purely for implementation simplicity.
bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(*mf.getFunction()))
if (skipFunction(mf.getFunction()))
return false;
if (EnableMachineSched.getNumOccurrences()) {
@ -389,7 +389,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
}
bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (skipFunction(*mf.getFunction()))
if (skipFunction(mf.getFunction()))
return false;
if (EnablePostRAMachineSched.getNumOccurrences()) {

2
llvm/lib/CodeGen/MachineSink.cpp
View File

@ -292,7 +292,7 @@ MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
}
bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "******** Machine Sinking ********\n");

4
llvm/lib/CodeGen/MachineVerifier.cpp
View File

@ -637,12 +637,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
const MCAsmInfo *AsmInfo = TM->getMCAsmInfo();
const BasicBlock *BB = MBB->getBasicBlock();
const Function *Fn = MF->getFunction();
const Function &F = MF->getFunction();
if (LandingPadSuccs.size() > 1 &&
!(AsmInfo &&
AsmInfo->getExceptionHandlingType() == ExceptionHandling::SjLj &&
BB && isa<SwitchInst>(BB->getTerminator())) &&
!isFuncletEHPersonality(classifyEHPersonality(Fn->getPersonalityFn())))
!isFuncletEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
report("MBB has more than one landing pad successor", MBB);
// Call AnalyzeBranch. If it succeeds, there several more conditions to check.

2
llvm/lib/CodeGen/OptimizePHIs.cpp
View File

@ -72,7 +72,7 @@ INITIALIZE_PASS(OptimizePHIs, DEBUG_TYPE,
"Optimize machine instruction PHIs", false, false)
bool OptimizePHIs::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(*Fn.getFunction()))
if (skipFunction(Fn.getFunction()))
return false;
MRI = &Fn.getRegInfo();

4
llvm/lib/CodeGen/PatchableFunction.cpp
View File

@ -54,11 +54,11 @@ static bool doesNotGeneratecode(const MachineInstr &MI) {
}
bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) {
if (!MF.getFunction()->hasFnAttribute("patchable-function"))
if (!MF.getFunction().hasFnAttribute("patchable-function"))
return false;
#ifndef NDEBUG
Attribute PatchAttr = MF.getFunction()->getFnAttribute("patchable-function");
Attribute PatchAttr = MF.getFunction().getFnAttribute("patchable-function");
StringRef PatchType = PatchAttr.getValueAsString();
assert(PatchType == "prologue-short-redirect" && "Only possibility today!");
#endif

2
llvm/lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -1662,7 +1662,7 @@ bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
}
bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");

2
llvm/lib/CodeGen/PostRASchedulerList.cpp
View File

@ -279,7 +279,7 @@ bool PostRAScheduler::enablePostRAScheduler(
}
bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(*Fn.getFunction()))
if (skipFunction(Fn.getFunction()))
return false;
TII = Fn.getSubtarget().getInstrInfo();

16
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -171,7 +171,7 @@ using StackObjSet = SmallSetVector<int, 8>;
/// runOnMachineFunction - Insert prolog/epilog code and replace abstract
/// frame indexes with appropriate references.
bool PEI::runOnMachineFunction(MachineFunction &Fn) {
const Function* F = Fn.getFunction();
const Function &F = Fn.getFunction();
const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
@ -206,7 +206,7 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) {
// called functions. Because of this, calculateCalleeSavedRegisters()
// must be called before this function in order to set the AdjustsStack
// and MaxCallFrameSize variables.
if (!F->hasFnAttribute(Attribute::Naked))
if (!F.hasFnAttribute(Attribute::Naked))
insertPrologEpilogCode(Fn);
// Replace all MO_FrameIndex operands with physical register references
@ -224,8 +224,8 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) {
MachineFrameInfo &MFI = Fn.getFrameInfo();
uint64_t StackSize = MFI.getStackSize();
if (WarnStackSize.getNumOccurrences() > 0 && WarnStackSize < StackSize) {
DiagnosticInfoStackSize DiagStackSize(*F, StackSize);
F->getContext().diagnose(DiagStackSize);
DiagnosticInfoStackSize DiagStackSize(F, StackSize);
F.getContext().diagnose(DiagStackSize);
}
delete RS;
@ -508,7 +508,7 @@ void PEI::spillCalleeSavedRegs(MachineFunction &Fn) {
assert(Fn.getProperties().hasProperty(
MachineFunctionProperties::Property::NoVRegs));
const Function *F = Fn.getFunction();
const Function &F = Fn.getFunction();
const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering();
MachineFrameInfo &MFI = Fn.getFrameInfo();
MinCSFrameIndex = std::numeric_limits<unsigned>::max();
@ -522,7 +522,7 @@ void PEI::spillCalleeSavedRegs(MachineFunction &Fn) {
assignCalleeSavedSpillSlots(Fn, SavedRegs, MinCSFrameIndex, MaxCSFrameIndex);
// Add the code to save and restore the callee saved registers.
if (!F->hasFnAttribute(Attribute::Naked)) {
if (!F.hasFnAttribute(Attribute::Naked)) {
MFI.setCalleeSavedInfoValid(true);
std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
@ -952,7 +952,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
ORE->emit([&]() {
return MachineOptimizationRemarkAnalysis(DEBUG_TYPE, "StackSize",
Fn.getFunction()->getSubprogram(),
Fn.getFunction().getSubprogram(),
&Fn.front())
<< ore::NV("NumStackBytes", StackSize) << " stack bytes in function";
});
@ -993,7 +993,7 @@ void PEI::insertPrologEpilogCode(MachineFunction &Fn) {
// approach is rather similar to that of Segmented Stacks, but it uses a
// different conditional check and another BIF for allocating more stack
// space.
if (Fn.getFunction()->getCallingConv() == CallingConv::HiPE)
if (Fn.getFunction().getCallingConv() == CallingConv::HiPE)
for (MachineBasicBlock *SaveBlock : SaveBlocks)
TFI.adjustForHiPEPrologue(Fn, *SaveBlock);
}

2
llvm/lib/CodeGen/RegAllocGreedy.cpp
View File

@ -2642,7 +2642,7 @@ bool RAGreedy::tryRecoloringCandidates(PQueue &RecoloringQueue,
unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
SmallVectorImpl<unsigned> &NewVRegs) {
CutOffInfo = CO_None;
LLVMContext &Ctx = MF->getFunction()->getContext();
LLVMContext &Ctx = MF->getFunction().getContext();
SmallVirtRegSet FixedRegisters;
unsigned Reg = selectOrSplitImpl(VirtReg, NewVRegs, FixedRegisters);
if (Reg == ~0U && (CutOffInfo != CO_None)) {

2
llvm/lib/CodeGen/RegAllocPBQP.cpp
View File

@ -799,7 +799,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) {
findVRegIntervalsToAlloc(MF, LIS);
#ifndef NDEBUG
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
std::string FullyQualifiedName =
F.getParent()->getModuleIdentifier() + "." + F.getName().str();
#endif

6
llvm/lib/CodeGen/RegUsageInfoCollector.cpp
View File

@ -95,7 +95,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
RegMask.resize(RegMaskSize, 0xFFFFFFFF);
const Function *F = MF.getFunction();
const Function &F = MF.getFunction();
PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
@ -127,7 +127,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
if (!TargetFrameLowering::isSafeForNoCSROpt(F)) {
const uint32_t *CallPreservedMask =
TRI->getCallPreservedMask(MF, F->getCallingConv());
TRI->getCallPreservedMask(MF, F.getCallingConv());
if (CallPreservedMask) {
// Set callee saved register as preserved.
for (unsigned i = 0; i < RegMaskSize; ++i)
@ -145,7 +145,7 @@ bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << " \n----------------------------------------\n");
PRUI->storeUpdateRegUsageInfo(F, std::move(RegMask));
PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask));
return false;
}

2
llvm/lib/CodeGen/RegUsageInfoPropagate.cpp
View File

@ -102,7 +102,7 @@ static const Function *findCalledFunction(const Module &M, MachineInstr &MI) {
}
bool RegUsageInfoPropagationPass::runOnMachineFunction(MachineFunction &MF) {
const Module *M = MF.getFunction()->getParent();
const Module *M = MF.getFunction().getParent();
PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
DEBUG(dbgs() << " ++++++++++++++++++++ " << getPassName()

2
llvm/lib/CodeGen/ResetMachineFunctionPass.cpp
View File

@ -51,7 +51,7 @@ namespace {
++NumFunctionsReset;
MF.reset();
if (EmitFallbackDiag) {
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
DiagnosticInfoISelFallback DiagFallback(F);
F.getContext().diagnose(DiagFallback);
}

2
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -114,7 +114,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
: ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()),
RemoveKillFlags(RemoveKillFlags),
UnknownValue(UndefValue::get(
Type::getVoidTy(mf.getFunction()->getContext()))) {
Type::getVoidTy(mf.getFunction().getContext()))) {
DbgValues.clear();
const TargetSubtargetInfo &ST = mf.getSubtarget();

14
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -161,7 +161,7 @@ namespace {
DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOpt::Level OL)
: DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes),
OptLevel(OL), AA(AA) {
ForCodeSize = DAG.getMachineFunction().getFunction()->optForSize();
ForCodeSize = DAG.getMachineFunction().getFunction().optForSize();
MaximumLegalStoreInBits = 0;
for (MVT VT : MVT::all_valuetypes())
@ -2933,7 +2933,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
// If integer divide is expensive and we satisfy the requirements, emit an
// alternate sequence. Targets may check function attributes for size/speed
// trade-offs.
AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
if (SDValue Op = BuildSDIV(N))
return Op;
@ -3004,7 +3004,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
}
// fold (udiv x, c) -> alternate
AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (N1C && !TLI.isIntDivCheap(N->getValueType(0), Attr))
if (SDValue Op = BuildUDIV(N))
return Op;
@ -3063,7 +3063,7 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
}
}
AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
// If X/C can be simplified by the division-by-constant logic, lower
// X%C to the equivalent of X-X/C*C.
@ -12940,7 +12940,7 @@ bool DAGCombiner::MergeConsecutiveStores(StoreSDNode *St) {
if (MemVT.getSizeInBits() * 2 > MaximumLegalStoreInBits)
return false;
bool NoVectors = DAG.getMachineFunction().getFunction()->hasFnAttribute(
bool NoVectors = DAG.getMachineFunction().getFunction().hasFnAttribute(
Attribute::NoImplicitFloat);
// This function cannot currently deal with non-byte-sized memory sizes.
@ -16986,7 +16986,7 @@ SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
SDValue DAGCombiner::BuildSDIV(SDNode *N) {
// when optimising for minimum size, we don't want to expand a div to a mul
// and a shift.
if (DAG.getMachineFunction().getFunction()->optForMinSize())
if (DAG.getMachineFunction().getFunction().optForMinSize())
return SDValue();
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
@ -17032,7 +17032,7 @@ SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
SDValue DAGCombiner::BuildUDIV(SDNode *N) {
// when optimising for minimum size, we don't want to expand a div to a mul
// and a shift.
if (DAG.getMachineFunction().getFunction()->optForMinSize())
if (DAG.getMachineFunction().getFunction().optForMinSize())
return SDValue();
ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));

4
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -2014,10 +2014,10 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
// isTailCall may be true since the callee does not reference caller stack
// frame. Check if it's in the right position and that the return types match.
SDValue TCChain = InChain;
const Function *F = DAG.getMachineFunction().getFunction();
const Function &F = DAG.getMachineFunction().getFunction();
bool isTailCall =
TLI.isInTailCallPosition(DAG, Node, TCChain) &&
(RetTy == F->getReturnType() || F->getReturnType()->isVoidTy());
(RetTy == F.getReturnType() || F.getReturnType()->isVoidTy());
if (isTailCall)
InChain = TCChain;

8
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -909,7 +909,7 @@ void SelectionDAG::init(MachineFunction &NewMF,
ORE = &NewORE;
TLI = getSubtarget().getTargetLowering();
TSI = getSubtarget().getSelectionDAGInfo();
Context = &MF->getFunction()->getContext();
Context = &MF->getFunction().getContext();
}
SelectionDAG::~SelectionDAG() {
@ -1331,7 +1331,7 @@ SDValue SelectionDAG::getConstantPool(const Constant *C, EVT VT,
assert((TargetFlags == 0 || isTarget) &&
"Cannot set target flags on target-independent globals");
if (Alignment == 0)
Alignment = MF->getFunction()->optForSize()
Alignment = MF->getFunction().optForSize()
? getDataLayout().getABITypeAlignment(C->getType())
: getDataLayout().getPrefTypeAlignment(C->getType());
unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool;
@ -5100,8 +5100,8 @@ static bool shouldLowerMemFuncForSize(const MachineFunction &MF) {
// On Darwin, -Os means optimize for size without hurting performance, so
// only really optimize for size when -Oz (MinSize) is used.
if (MF.getTarget().getTargetTriple().isOSDarwin())
return MF.getFunction()->optForMinSize();
return MF.getFunction()->optForSize();
return MF.getFunction().optForMinSize();
return MF.getFunction().optForSize();
}
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,

22
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -1573,9 +1573,9 @@ void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
EVT(TLI.getPointerTy(DL))));
}
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
bool isVarArg = DAG.getMachineFunction().getFunction().isVarArg();
CallingConv::ID CallConv =
DAG.getMachineFunction().getFunction()->getCallingConv();
DAG.getMachineFunction().getFunction().getCallingConv();
Chain = DAG.getTargetLoweringInfo().LowerReturn(
Chain, CallConv, isVarArg, Outs, OutVals, getCurSDLoc(), DAG);
@ -2110,7 +2110,7 @@ static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL,
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
MachineFunction &MF = DAG.getMachineFunction();
Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent());
Value *Global = TLI.getSDagStackGuard(*MF.getFunction().getParent());
MachineSDNode *Node =
DAG.getMachineNode(TargetOpcode::LOAD_STACK_GUARD, DL, PtrTy, Chain);
if (Global) {
@ -2144,7 +2144,7 @@ void SelectionDAGBuilder::visitSPDescriptorParent(StackProtectorDescriptor &SPD,
SDValue Guard;
SDLoc dl = getCurSDLoc();
SDValue StackSlotPtr = DAG.getFrameIndex(FI, PtrTy);
const Module &M = *ParentBB->getParent()->getFunction()->getParent();
const Module &M = *ParentBB->getParent()->getFunction().getParent();
unsigned Align = DL->getPrefTypeAlignment(Type::getInt8PtrTy(M.getContext()));
// Generate code to load the content of the guard slot.
@ -4766,8 +4766,8 @@ static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS,
if (Val == 0)
return DAG.getConstantFP(1.0, DL, LHS.getValueType());
const Function *F = DAG.getMachineFunction().getFunction();
if (!F->optForSize() ||
const Function &F = DAG.getMachineFunction().getFunction();
if (!F.optForSize() ||
// If optimizing for size, don't insert too many multiplies.
// This inserts up to 5 multiplies.
countPopulation(Val) + Log2_32(Val) < 7) {
@ -5640,7 +5640,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
case Intrinsic::stackguard: {
EVT PtrTy = TLI.getPointerTy(DAG.getDataLayout());
MachineFunction &MF = DAG.getMachineFunction();
const Module &M = *MF.getFunction()->getParent();
const Module &M = *MF.getFunction().getParent();
SDValue Chain = getRoot();
if (TLI.useLoadStackGuardNode()) {
Res = getLoadStackGuard(DAG, sdl, Chain);
@ -5748,9 +5748,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
return nullptr;
case Intrinsic::gcroot: {
MachineFunction &MF = DAG.getMachineFunction();
const Function *F = MF.getFunction();
(void)F;
assert(F->hasGC() &&
assert(MF.getFunction().hasGC() &&
"only valid in functions with gc specified, enforced by Verifier");
assert(GFI && "implied by previous");
const Value *Alloca = I.getArgOperand(0)->stripPointerCasts();
@ -9869,7 +9867,7 @@ MachineBasicBlock *SelectionDAGBuilder::peelDominantCaseCluster(
// Don't perform if there is only one cluster or optimizing for size.
if (SwitchPeelThreshold > 100 || !FuncInfo.BPI || Clusters.size() < 2 ||
TM.getOptLevel() == CodeGenOpt::None ||
SwitchMBB->getParent()->getFunction()->optForMinSize())
SwitchMBB->getParent()->getFunction().optForMinSize())
return SwitchMBB;
BranchProbability TopCaseProb = BranchProbability(SwitchPeelThreshold, 100);
@ -10021,7 +10019,7 @@ void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
unsigned NumClusters = W.LastCluster - W.FirstCluster + 1;
if (NumClusters > 3 && TM.getOptLevel() != CodeGenOpt::None &&
!DefaultMBB->getParent()->getFunction()->optForMinSize()) {
!DefaultMBB->getParent()->getFunction().optForMinSize()) {
// For optimized builds, lower large range as a balanced binary tree.
splitWorkItem(WorkList, W, SI.getCondition(), SwitchMBB);
continue;

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -212,7 +212,7 @@ namespace llvm {
IS.OptLevel = NewOptLevel;
IS.TM.setOptLevel(NewOptLevel);
DEBUG(dbgs() << "\nChanging optimization level for Function "
<< IS.MF->getFunction()->getName() << "\n");
<< IS.MF->getFunction().getName() << "\n");
DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel
<< " ; After: -O" << NewOptLevel << "\n");
SavedFastISel = IS.TM.Options.EnableFastISel;
@ -228,7 +228,7 @@ namespace llvm {
if (IS.OptLevel == SavedOptLevel)
return;
DEBUG(dbgs() << "\nRestoring optimization level for Function "
<< IS.MF->getFunction()->getName() << "\n");
<< IS.MF->getFunction().getName() << "\n");
DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel
<< " ; After: -O" << SavedOptLevel << "\n");
IS.OptLevel = SavedOptLevel;
@ -384,7 +384,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
assert((!EnableFastISelAbort || TM.Options.EnableFastISel) &&
"-fast-isel-abort > 0 requires -fast-isel");
const Function &Fn = *mf.getFunction();
const Function &Fn = mf.getFunction();
MF = &mf;
// Reset the target options before resetting the optimization

6
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -52,11 +52,11 @@ bool TargetLowering::isPositionIndependent() const {
/// so, it sets Chain to the input chain of the tail call.
bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
SDValue &Chain) const {
const Function *F = DAG.getMachineFunction().getFunction();
const Function &F = DAG.getMachineFunction().getFunction();
// Conservatively require the attributes of the call to match those of
// the return. Ignore noalias because it doesn't affect the call sequence.
AttributeList CallerAttrs = F->getAttributes();
AttributeList CallerAttrs = F.getAttributes();
if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
.removeAttribute(Attribute::NoAlias)
.hasAttributes())
@ -2963,7 +2963,7 @@ static SDValue BuildExactSDIV(const TargetLowering &TLI, SDValue Op1, APInt d,
SDValue TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG,
std::vector<SDNode *> *Created) const {
AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLI.isIntDivCheap(N->getValueType(0), Attr))
return SDValue(N,0); // Lower SDIV as SDIV

10
llvm/lib/CodeGen/ShrinkWrap.cpp
View File

@ -449,7 +449,7 @@ static bool isIrreducibleCFG(const MachineFunction &MF,
}
bool ShrinkWrap::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()) || MF.empty() || !isShrinkWrapEnabled(MF))
if (skipFunction(MF.getFunction()) || MF.empty() || !isShrinkWrapEnabled(MF))
return false;
DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
@ -569,10 +569,10 @@ bool ShrinkWrap::isShrinkWrapEnabled(const MachineFunction &MF) {
// of the crash. Since a crash can happen anywhere, the
// frame must be lowered before anything else happen for the
// sanitizers to be able to get a correct stack frame.
!(MF.getFunction()->hasFnAttribute(Attribute::SanitizeAddress) ||
MF.getFunction()->hasFnAttribute(Attribute::SanitizeThread) ||
MF.getFunction()->hasFnAttribute(Attribute::SanitizeMemory) ||
MF.getFunction()->hasFnAttribute(Attribute::SanitizeHWAddress));
!(MF.getFunction().hasFnAttribute(Attribute::SanitizeAddress) ||
MF.getFunction().hasFnAttribute(Attribute::SanitizeThread) ||
MF.getFunction().hasFnAttribute(Attribute::SanitizeMemory) ||
MF.getFunction().hasFnAttribute(Attribute::SanitizeHWAddress));
// If EnableShrinkWrap is set, it takes precedence on whatever the
// target sets. The rational is that we assume we want to test
// something related to shrink-wrapping.

5
llvm/lib/CodeGen/StackColoring.cpp
View File

@ -1129,8 +1129,7 @@ void StackColoring::expungeSlotMap(DenseMap<int, int> &SlotRemap,
bool StackColoring::runOnMachineFunction(MachineFunction &Func) {
DEBUG(dbgs() << "********** Stack Coloring **********\n"
<< "********** Function: "
<< ((const Value*)Func.getFunction())->getName() << '\n');
<< "********** Function: " << Func.getName() << '\n');
MF = &Func;
MFI = &MF->getFrameInfo();
Indexes = &getAnalysis<SlotIndexes>();
@ -1170,7 +1169,7 @@ bool StackColoring::runOnMachineFunction(MachineFunction &Func) {
// Don't continue because there are not enough lifetime markers, or the
// stack is too small, or we are told not to optimize the slots.
if (NumMarkers < 2 || TotalSize < 16 || DisableColoring ||
skipFunction(*Func.getFunction())) {
skipFunction(Func.getFunction())) {
DEBUG(dbgs()<<"Will not try to merge slots.\n");
return removeAllMarkers();
}

2
llvm/lib/CodeGen/TailDuplication.cpp
View File

@ -49,7 +49,7 @@ char &llvm::TailDuplicateID = TailDuplicatePass::ID;
INITIALIZE_PASS(TailDuplicatePass, DEBUG_TYPE, "Tail Duplication", false, false)
bool TailDuplicatePass::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
auto MBPI = &getAnalysis<MachineBranchProbabilityInfo>();

2
llvm/lib/CodeGen/TailDuplicator.cpp
View File

@ -550,7 +550,7 @@ bool TailDuplicator::shouldTailDuplicate(bool IsSimple,
unsigned MaxDuplicateCount;
if (TailDupSize == 0 &&
TailDuplicateSize.getNumOccurrences() == 0 &&
MF->getFunction()->optForSize())
MF->getFunction().optForSize())
MaxDuplicateCount = 1;
else if (TailDupSize == 0)
MaxDuplicateCount = TailDuplicateSize;

6
llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp
View File

@ -32,7 +32,7 @@ TargetFrameLowering::~TargetFrameLowering() = default;
/// The default implementation just looks at attribute "no-frame-pointer-elim".
bool TargetFrameLowering::noFramePointerElim(const MachineFunction &MF) const {
auto Attr = MF.getFunction()->getFnAttribute("no-frame-pointer-elim");
auto Attr = MF.getFunction().getFnAttribute("no-frame-pointer-elim");
return Attr.getValueAsString() == "true";
}
@ -82,7 +82,7 @@ void TargetFrameLowering::determineCalleeSaves(MachineFunction &MF,
return;
// In Naked functions we aren't going to save any registers.
if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
if (MF.getFunction().hasFnAttribute(Attribute::Naked))
return;
// Functions which call __builtin_unwind_init get all their registers saved.
@ -99,7 +99,7 @@ unsigned TargetFrameLowering::getStackAlignmentSkew(
const MachineFunction &MF) const {
// When HHVM function is called, the stack is skewed as the return address
// is removed from the stack before we enter the function.
if (LLVM_UNLIKELY(MF.getFunction()->getCallingConv() == CallingConv::HHVM))
if (LLVM_UNLIKELY(MF.getFunction().getCallingConv() == CallingConv::HHVM))
return MF.getTarget().getPointerSize();
return 0;

4
llvm/lib/CodeGen/TargetLoweringBase.cpp
View File

@ -1592,8 +1592,8 @@ void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) {
/// Get the reciprocal estimate attribute string for a function that will
/// override the target defaults.
static StringRef getRecipEstimateForFunc(MachineFunction &MF) {
const Function *F = MF.getFunction();
return F->getFnAttribute("reciprocal-estimates").getValueAsString();
const Function &F = MF.getFunction();
return F.getFnAttribute("reciprocal-estimates").getValueAsString();
}
/// Construct a string for the given reciprocal operation of the given type.

2
llvm/lib/CodeGen/TargetOptionsImpl.cpp
View File

@ -28,7 +28,7 @@ bool TargetOptions::DisableFramePointerElim(const MachineFunction &MF) const {
return true;
// Check to see if we should eliminate non-leaf frame pointers.
if (MF.getFunction()->hasFnAttribute("no-frame-pointer-elim-non-leaf"))
if (MF.getFunction().hasFnAttribute("no-frame-pointer-elim-non-leaf"))
return MF.getFrameInfo().hasCalls();
return false;

10
llvm/lib/CodeGen/TargetRegisterInfo.cpp
View File

@ -422,21 +422,21 @@ TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
}
bool TargetRegisterInfo::canRealignStack(const MachineFunction &MF) const {
return !MF.getFunction()->hasFnAttribute("no-realign-stack");
return !MF.getFunction().hasFnAttribute("no-realign-stack");
}
bool TargetRegisterInfo::needsStackRealignment(
const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo();
const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
const Function *F = MF.getFunction();
const Function &F = MF.getFunction();
unsigned StackAlign = TFI->getStackAlignment();
bool requiresRealignment = ((MFI.getMaxAlignment() > StackAlign) ||
F->hasFnAttribute(Attribute::StackAlignment));
if (MF.getFunction()->hasFnAttribute("stackrealign") || requiresRealignment) {
F.hasFnAttribute(Attribute::StackAlignment));
if (F.hasFnAttribute("stackrealign") || requiresRealignment) {
if (canRealignStack(MF))
return true;
DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n");
DEBUG(dbgs() << "Can't realign function's stack: " << F.getName() << "\n");
}
return false;
}

2
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1663,7 +1663,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
OptLevel = TM.getOptLevel();
// Disable optimizations if requested. We cannot skip the whole pass as some
// fixups are necessary for correctness.
if (skipFunction(*Func.getFunction()))
if (skipFunction(Func.getFunction()))
OptLevel = CodeGenOpt::None;
bool MadeChange = false;

2
llvm/lib/CodeGen/XRayInstrumentation.cpp
View File

@ -142,7 +142,7 @@ void XRayInstrumentation::prependRetWithPatchableExit(
}
bool XRayInstrumentation::runOnMachineFunction(MachineFunction &MF) {
auto &F = *MF.getFunction();
auto &F = MF.getFunction();
auto InstrAttr = F.getFnAttribute("function-instrument");
bool AlwaysInstrument = !InstrAttr.hasAttribute(Attribute::None) &&
InstrAttr.isStringAttribute() &&

2
llvm/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
View File

@ -308,7 +308,7 @@ public:
//===----------------------------------------------------------------------===//
bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) {
if (skipFunction(*F.getFunction()))
if (skipFunction(F.getFunction()))
return false;
if (!F.getSubtarget<AArch64Subtarget>().balanceFPOps())

2
llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
View File

@ -393,7 +393,7 @@ bool AArch64AdvSIMDScalar::runOnMachineFunction(MachineFunction &mf) {
bool Changed = false;
DEBUG(dbgs() << "***** AArch64AdvSIMDScalar *****\n");
if (skipFunction(*mf.getFunction()))
if (skipFunction(mf.getFunction()))
return false;
MRI = &mf.getRegInfo();

4
llvm/lib/Target/AArch64/AArch64CallLowering.cpp
View File

@ -220,7 +220,7 @@ void AArch64CallLowering::splitToValueTypes(
bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
const Value *Val, unsigned VReg) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg");
@ -322,7 +322,7 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const ArgInfo &OrigRet,
ArrayRef<ArgInfo> OrigArgs) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
MachineRegisterInfo &MRI = MF.getRegInfo();
auto &DL = F.getParent()->getDataLayout();

2
llvm/lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
View File

@ -42,7 +42,7 @@ struct LDTLSCleanup : public MachineFunctionPass {
}
bool runOnMachineFunction(MachineFunction &MF) override {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();

2
llvm/lib/Target/AArch64/AArch64CollectLOH.cpp
View File

@ -482,7 +482,7 @@ static void handleNormalInst(const MachineInstr &MI, LOHInfo *LOHInfos) {
}
bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "********** AArch64 Collect LOH **********\n"

2
llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
View File

@ -290,7 +290,7 @@ bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI,
}
bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "********** AArch64 Conditional Branch Tuning **********\n"

2
llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
View File

@ -327,7 +327,7 @@ bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI,
bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
<< "********** Function: " << MF.getName() << '\n');
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TII = MF.getSubtarget().getInstrInfo();

4
llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
View File

@ -924,7 +924,7 @@ bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) {
bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
<< "********** Function: " << MF.getName() << '\n');
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TII = MF.getSubtarget().getInstrInfo();
@ -936,7 +936,7 @@ bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) {
MBPI = &getAnalysis<MachineBranchProbabilityInfo>();
Traces = &getAnalysis<MachineTraceMetrics>();
MinInstr = nullptr;
MinSize = MF.getFunction()->optForMinSize();
MinSize = MF.getFunction().optForMinSize();
bool Changed = false;
CmpConv.runOnMachineFunction(MF, MBPI);

2
llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
View File

@ -198,7 +198,7 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock(
// Scan the function for instructions that have a dead definition of a
// register. Replace that register with the zero register when possible.
bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TRI = MF.getSubtarget().getRegisterInfo();

2
llvm/lib/Target/AArch64/AArch64FalkorHWPFFix.cpp
View File

@ -798,7 +798,7 @@ bool FalkorHWPFFix::runOnMachineFunction(MachineFunction &Fn) {
if (ST.getProcFamily() != AArch64Subtarget::Falkor)
return false;
if (skipFunction(*Fn.getFunction()))
if (skipFunction(Fn.getFunction()))
return false;
TII = static_cast<const AArch64InstrInfo *>(ST.getInstrInfo());

22
llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
View File

@ -174,7 +174,7 @@ bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
return false;
// Don't use the red zone if the function explicitly asks us not to.
// This is typically used for kernel code.
if (MF.getFunction()->hasFnAttribute(Attribute::NoRedZone))
if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone))
return false;
const MachineFrameInfo &MFI = MF.getFrameInfo();
@ -459,13 +459,13 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
MachineBasicBlock &MBB) const {
MachineBasicBlock::iterator MBBI = MBB.begin();
const MachineFrameInfo &MFI = MF.getFrameInfo();
const Function *Fn = MF.getFunction();
const Function &F = MF.getFunction();
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
MachineModuleInfo &MMI = MF.getMMI();
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry();
bool needsFrameMoves = MMI.hasDebugInfo() || F.needsUnwindTableEntry();
bool HasFP = hasFP(MF);
// Debug location must be unknown since the first debug location is used
@ -474,7 +474,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
// All calls are tail calls in GHC calling conv, and functions have no
// prologue/epilogue.
if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
return;
int NumBytes = (int)MFI.getStackSize();
@ -507,7 +507,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
}
bool IsWin64 =
Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv());
Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject;
@ -716,7 +716,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
// All calls are tail calls in GHC calling conv, and functions have no
// prologue/epilogue.
if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
return;
// Initial and residual are named for consistency with the prologue. Note that
@ -765,7 +765,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
// it as the 2nd argument of AArch64ISD::TC_RETURN.
bool IsWin64 =
Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv());
Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
auto PrologueSaveSize = AFI->getCalleeSavedStackSize() + FixedObject;
@ -857,7 +857,7 @@ int AArch64FrameLowering::resolveFrameIndexReference(const MachineFunction &MF,
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
bool IsWin64 =
Subtarget.isCallingConvWin64(MF.getFunction()->getCallingConv());
Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
int FPOffset = MFI.getObjectOffset(FI) + FixedObject + 16;
int Offset = MFI.getObjectOffset(FI) + MFI.getStackSize();
@ -928,7 +928,7 @@ static unsigned getPrologueDeath(MachineFunction &MF, unsigned Reg) {
static bool produceCompactUnwindFrame(MachineFunction &MF) {
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
AttributeList Attrs = MF.getFunction()->getAttributes();
AttributeList Attrs = MF.getFunction().getAttributes();
return Subtarget.isTargetMachO() &&
!(Subtarget.getTargetLowering()->supportSwiftError() &&
Attrs.hasAttrSomewhere(Attribute::SwiftError));
@ -959,7 +959,7 @@ static void computeCalleeSaveRegisterPairs(
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
MachineFrameInfo &MFI = MF.getFrameInfo();
CallingConv::ID CC = MF.getFunction()->getCallingConv();
CallingConv::ID CC = MF.getFunction().getCallingConv();
unsigned Count = CSI.size();
(void)CC;
// MachO's compact unwind format relies on all registers being stored in
@ -1154,7 +1154,7 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
RegScavenger *RS) const {
// All calls are tail calls in GHC calling conv, and functions have no
// prologue/epilogue.
if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
if (MF.getFunction().getCallingConv() == CallingConv::GHC)
return;
TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);

2
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
View File

@ -53,7 +53,7 @@ public:
}
bool runOnMachineFunction(MachineFunction &MF) override {
ForCodeSize = MF.getFunction()->optForSize();
ForCodeSize = MF.getFunction().optForSize();
Subtarget = &MF.getSubtarget<AArch64Subtarget>();
return SelectionDAGISel::runOnMachineFunction(MF);
}

28
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -2731,7 +2731,7 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo &MFI = MF.getFrameInfo();
bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv());
bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
@ -2745,7 +2745,7 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
// we use a special version of AnalyzeFormalArguments to pass in ValVT and
// LocVT.
unsigned NumArgs = Ins.size();
Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
Function::const_arg_iterator CurOrigArg = MF.getFunction().arg_begin();
unsigned CurArgIdx = 0;
for (unsigned i = 0; i != NumArgs; ++i) {
MVT ValVT = Ins[i].VT;
@ -2935,7 +2935,7 @@ void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
MachineFrameInfo &MFI = MF.getFrameInfo();
AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
auto PtrVT = getPointerTy(DAG.getDataLayout());
bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv());
bool IsWin64 = Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv());
SmallVector<SDValue, 8> MemOps;
@ -3087,15 +3087,15 @@ bool AArch64TargetLowering::isEligibleForTailCallOptimization(
return false;
MachineFunction &MF = DAG.getMachineFunction();
const Function *CallerF = MF.getFunction();
CallingConv::ID CallerCC = CallerF->getCallingConv();
const Function &CallerF = MF.getFunction();
CallingConv::ID CallerCC = CallerF.getCallingConv();
bool CCMatch = CallerCC == CalleeCC;
// Byval parameters hand the function a pointer directly into the stack area
// we want to reuse during a tail call. Working around this *is* possible (see
// X86) but less efficient and uglier in LowerCall.
for (Function::const_arg_iterator i = CallerF->arg_begin(),
e = CallerF->arg_end();
for (Function::const_arg_iterator i = CallerF.arg_begin(),
e = CallerF.arg_end();
i != e; ++i)
if (i->hasByValAttr())
return false;
@ -4185,7 +4185,7 @@ SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
}
SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
if (DAG.getMachineFunction().getFunction()->hasFnAttribute(
if (DAG.getMachineFunction().getFunction().hasFnAttribute(
Attribute::NoImplicitFloat))
return SDValue();
@ -4668,7 +4668,7 @@ SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
if (Subtarget->isCallingConvWin64(MF.getFunction()->getCallingConv()))
if (Subtarget->isCallingConvWin64(MF.getFunction().getCallingConv()))
return LowerWin64_VASTART(Op, DAG);
else if (Subtarget->isTargetDarwin())
return LowerDarwin_VASTART(Op, DAG);
@ -7909,9 +7909,9 @@ EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
// instruction to materialize the v2i64 zero and one store (with restrictive
// addressing mode). Just do two i64 store of zero-registers.
bool Fast;
const Function *F = MF.getFunction();
const Function &F = MF.getFunction();
if (Subtarget->hasFPARMv8() && !IsMemset && Size >= 16 &&
!F->hasFnAttribute(Attribute::NoImplicitFloat) &&
!F.hasFnAttribute(Attribute::NoImplicitFloat) &&
(memOpAlign(SrcAlign, DstAlign, 16) ||
(allowsMisalignedMemoryAccesses(MVT::f128, 0, 1, &Fast) && Fast)))
return MVT::f128;
@ -8156,7 +8156,7 @@ SDValue
AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
SelectionDAG &DAG,
std::vector<SDNode *> *Created) const {
AttributeList Attr = DAG.getMachineFunction().getFunction()->getAttributes();
AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
if (isIntDivCheap(N->getValueType(0), Attr))
return SDValue(N,0); // Lower SDIV as SDIV
@ -9577,7 +9577,7 @@ static SDValue splitStores(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
return SDValue();
// Don't split at -Oz.
if (DAG.getMachineFunction().getFunction()->optForMinSize())
if (DAG.getMachineFunction().getFunction().optForMinSize())
return SDValue();
// Don't split v2i64 vectors. Memcpy lowering produces those and splitting
@ -10939,7 +10939,7 @@ void AArch64TargetLowering::insertCopiesSplitCSR(
// fine for CXX_FAST_TLS since the C++-style TLS access functions should be
// nounwind. If we want to generalize this later, we may need to emit
// CFI pseudo-instructions.
assert(Entry->getParent()->getFunction()->hasFnAttribute(
assert(Entry->getParent()->getFunction().hasFnAttribute(
Attribute::NoUnwind) &&
"Function should be nounwind in insertCopiesSplitCSR!");
Entry->addLiveIn(*I);

6
llvm/lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -415,7 +415,7 @@ public:
// Do not merge to float value size (128 bytes) if no implicit
// float attribute is set.
bool NoFloat = DAG.getMachineFunction().getFunction()->hasFnAttribute(
bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
Attribute::NoImplicitFloat);
if (NoFloat)
@ -444,8 +444,8 @@ public:
}
bool supportSplitCSR(MachineFunction *MF) const override {
return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
}
void initializeSplitCSR(MachineBasicBlock *Entry) const override;
void insertCopiesSplitCSR(

10
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -4753,21 +4753,21 @@ AArch64InstrInfo::getOutlininingCandidateInfo(
bool AArch64InstrInfo::isFunctionSafeToOutlineFrom(MachineFunction &MF,
bool OutlineFromLinkOnceODRs) const {
const Function *F = MF.getFunction();
const Function &F = MF.getFunction();
// If F uses a redzone, then don't outline from it because it might mess up
// the stack.
if (!F->hasFnAttribute(Attribute::NoRedZone))
if (!F.hasFnAttribute(Attribute::NoRedZone))
return false;
// If anyone is using the address of this function, don't outline from it.
if (F->hasAddressTaken())
if (F.hasAddressTaken())
return false;
// Can F be deduplicated by the linker? If it can, don't outline from it.
if (!OutlineFromLinkOnceODRs && F->hasLinkOnceODRLinkage())
if (!OutlineFromLinkOnceODRs && F.hasLinkOnceODRLinkage())
return false;
return true;
}

6
llvm/lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -328,10 +328,10 @@ def AArch64umaxv : SDNode<"AArch64ISD::UMAXV", SDT_AArch64UnaryVec>;
// the Function object through the <Target>Subtarget and objections were raised
// to that (see post-commit review comments for r301750).
let RecomputePerFunction = 1 in {
def ForCodeSize : Predicate<"MF->getFunction()->optForSize()">;
def NotForCodeSize : Predicate<"!MF->getFunction()->optForSize()">;
def ForCodeSize : Predicate<"MF->getFunction().optForSize()">;
def NotForCodeSize : Predicate<"!MF->getFunction().optForSize()">;
// Avoid generating STRQro if it is slow, unless we're optimizing for code size.
def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction()->optForSize()">;
def UseSTRQro : Predicate<"!Subtarget->isSTRQroSlow() || MF->getFunction().optForSize()">;
}
include "AArch64InstrFormats.td"

2
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
View File

@ -1759,7 +1759,7 @@ bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
}
bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
if (skipFunction(*Fn.getFunction()))
if (skipFunction(Fn.getFunction()))
return false;
Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());

2
llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
View File

@ -485,7 +485,7 @@ bool AArch64RedundantCopyElimination::optimizeBlock(MachineBasicBlock *MBB) {
bool AArch64RedundantCopyElimination::runOnMachineFunction(
MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TRI = MF.getSubtarget().getRegisterInfo();
MRI = &MF.getRegInfo();

14
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
View File

@ -42,22 +42,22 @@ AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
const MCPhysReg *
AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
assert(MF && "Invalid MachineFunction pointer.");
if (MF->getFunction()->getCallingConv() == CallingConv::GHC)
if (MF->getFunction().getCallingConv() == CallingConv::GHC)
// GHC set of callee saved regs is empty as all those regs are
// used for passing STG regs around
return CSR_AArch64_NoRegs_SaveList;
if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
if (MF->getFunction().getCallingConv() == CallingConv::AnyReg)
return CSR_AArch64_AllRegs_SaveList;
if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS)
if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS)
return MF->getInfo<AArch64FunctionInfo>()->isSplitCSR() ?
CSR_AArch64_CXX_TLS_Darwin_PE_SaveList :
CSR_AArch64_CXX_TLS_Darwin_SaveList;
if (MF->getSubtarget<AArch64Subtarget>().getTargetLowering()
->supportSwiftError() &&
MF->getFunction()->getAttributes().hasAttrSomewhere(
MF->getFunction().getAttributes().hasAttrSomewhere(
Attribute::SwiftError))
return CSR_AArch64_AAPCS_SwiftError_SaveList;
if (MF->getFunction()->getCallingConv() == CallingConv::PreserveMost)
if (MF->getFunction().getCallingConv() == CallingConv::PreserveMost)
return CSR_AArch64_RT_MostRegs_SaveList;
else
return CSR_AArch64_AAPCS_SaveList;
@ -66,7 +66,7 @@ AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const MCPhysReg *AArch64RegisterInfo::getCalleeSavedRegsViaCopy(
const MachineFunction *MF) const {
assert(MF && "Invalid MachineFunction pointer.");
if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
if (MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
MF->getInfo<AArch64FunctionInfo>()->isSplitCSR())
return CSR_AArch64_CXX_TLS_Darwin_ViaCopy_SaveList;
return nullptr;
@ -84,7 +84,7 @@ AArch64RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
return CSR_AArch64_CXX_TLS_Darwin_RegMask;
if (MF.getSubtarget<AArch64Subtarget>().getTargetLowering()
->supportSwiftError() &&
MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
MF.getFunction().getAttributes().hasAttrSomewhere(Attribute::SwiftError))
return CSR_AArch64_AAPCS_SwiftError_RegMask;
if (CC == CallingConv::PreserveMost)
return CSR_AArch64_RT_MostRegs_RegMask;

2
llvm/lib/Target/AArch64/AArch64SIMDInstrOpt.cpp
View File

@ -690,7 +690,7 @@ unsigned AArch64SIMDInstrOpt::determineSrcReg(MachineInstr &MI) const {
}
bool AArch64SIMDInstrOpt::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
TII = MF.getSubtarget().getInstrInfo();

2
llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp
View File

@ -120,7 +120,7 @@ bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) {
}
bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(*MF.getFunction()))
if (skipFunction(MF.getFunction()))
return false;
const TargetSubtargetInfo &ST = MF.getSubtarget();

52
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
View File

@ -205,7 +205,7 @@ void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
return;
HSAMetadataStream.emitKernel(*MF->getFunction(),
HSAMetadataStream.emitKernel(MF->getFunction(),
getHSACodeProps(*MF, CurrentProgramInfo),
getHSADebugProps(*MF, CurrentProgramInfo));
}
@ -215,14 +215,14 @@ void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
const AMDGPUSubtarget &STM = MF->getSubtarget<AMDGPUSubtarget>();
if (MFI->isEntryFunction() && STM.isAmdCodeObjectV2(*MF)) {
SmallString<128> SymbolName;
getNameWithPrefix(SymbolName, MF->getFunction()),
getNameWithPrefix(SymbolName, &MF->getFunction()),
getTargetStreamer()->EmitAMDGPUSymbolType(
SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
}
const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
if (STI.dumpCode()) {
// Disassemble function name label to text.
DisasmLines.push_back(MF->getFunction()->getName().str() + ":");
DisasmLines.push_back(MF->getName().str() + ":");
DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
HexLines.push_back("");
}
@ -314,7 +314,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
getSIProgramInfo(CurrentProgramInfo, MF);
} else {
auto I = CallGraphResourceInfo.insert(
std::make_pair(MF.getFunction(), SIFunctionResourceInfo()));
std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
SIFunctionResourceInfo &Info = I.first->second;
assert(I.second && "should only be called once per function");
Info = analyzeResourceUsage(MF);
@ -343,7 +343,7 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
if (STM.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
if (!MFI->isEntryFunction()) {
OutStreamer->emitRawComment(" Function info:", false);
SIFunctionResourceInfo &Info = CallGraphResourceInfo[MF.getFunction()];
SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
emitCommonFunctionComments(
Info.NumVGPR,
Info.getTotalNumSGPRs(MF.getSubtarget<SISubtarget>()),
@ -469,7 +469,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
unsigned RsrcReg;
if (STM.getGeneration() >= R600Subtarget::EVERGREEN) {
// Evergreen / Northern Islands
switch (MF.getFunction()->getCallingConv()) {
switch (MF.getFunction().getCallingConv()) {
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
case CallingConv::AMDGPU_GS: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
@ -478,7 +478,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
}
} else {
// R600 / R700
switch (MF.getFunction()->getCallingConv()) {
switch (MF.getFunction().getCallingConv()) {
default: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_GS: LLVM_FALLTHROUGH;
case CallingConv::AMDGPU_CS: LLVM_FALLTHROUGH;
@ -493,7 +493,7 @@ void AMDGPUAsmPrinter::EmitProgramInfoR600(const MachineFunction &MF) {
OutStreamer->EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
OutStreamer->EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
OutStreamer->EmitIntValue(R_0288E8_SQ_LDS_ALLOC, 4);
OutStreamer->EmitIntValue(alignTo(MFI->getLDSSize(), 4) >> 2, 4);
}
@ -787,9 +787,9 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
if (!isUInt<32>(ProgInfo.ScratchSize)) {
DiagnosticInfoStackSize DiagStackSize(*MF.getFunction(),
DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
ProgInfo.ScratchSize, DS_Error);
MF.getFunction()->getContext().diagnose(DiagStackSize);
MF.getFunction().getContext().diagnose(DiagStackSize);
}
const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
@ -808,8 +808,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
// This can happen due to a compiler bug or when using inline asm.
LLVMContext &Ctx = MF.getFunction()->getContext();
DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
LLVMContext &Ctx = MF.getFunction().getContext();
DiagnosticInfoResourceLimit Diag(MF.getFunction(),
"addressable scalar registers",
ProgInfo.NumSGPR, DS_Error,
DK_ResourceLimit,
@ -836,8 +836,8 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
// This can happen due to a compiler bug or when using inline asm to use
// the registers which are usually reserved for vcc etc.
LLVMContext &Ctx = MF.getFunction()->getContext();
DiagnosticInfoResourceLimit Diag(*MF.getFunction(),
LLVMContext &Ctx = MF.getFunction().getContext();
DiagnosticInfoResourceLimit Diag(MF.getFunction(),
"scalar registers",
ProgInfo.NumSGPR, DS_Error,
DK_ResourceLimit,
@ -856,15 +856,15 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
}
if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
LLVMContext &Ctx = MF.getFunction()->getContext();
DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "user SGPRs",
LLVMContext &Ctx = MF.getFunction().getContext();
DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
MFI->getNumUserSGPRs(), DS_Error);
Ctx.diagnose(Diag);
}
if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
LLVMContext &Ctx = MF.getFunction()->getContext();
DiagnosticInfoResourceLimit Diag(*MF.getFunction(), "local memory",
LLVMContext &Ctx = MF.getFunction().getContext();
DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
MFI->getLDSSize(), DS_Error);
Ctx.diagnose(Diag);
}
@ -977,9 +977,9 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
const SIProgramInfo &CurrentProgramInfo) {
const SISubtarget &STM = MF.getSubtarget<SISubtarget>();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
unsigned RsrcReg = getRsrcReg(MF.getFunction()->getCallingConv());
unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
@ -997,13 +997,13 @@ void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
unsigned Rsrc2Val = 0;
if (STM.isVGPRSpillingEnabled(*MF.getFunction())) {
if (STM.isVGPRSpillingEnabled(MF.getFunction())) {
OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
OutStreamer->EmitIntValue(S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
Rsrc2Val = S_00B84C_SCRATCH_EN(CurrentProgramInfo.ScratchBlocks > 0);
}
if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
@ -1036,13 +1036,13 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
// we can use the same fixed value that .AMDGPU.config has for Mesa. Note
// that we use a register number rather than a byte offset, so we need to
// divide by 4.
unsigned Rsrc1Reg = getRsrcReg(MF.getFunction()->getCallingConv()) / 4;
unsigned Rsrc1Reg = getRsrcReg(MF.getFunction().getCallingConv()) / 4;
unsigned Rsrc2Reg = Rsrc1Reg + 1;
// Also calculate the PAL metadata key for *S_SCRATCH_SIZE. It can be used
// with a constant offset to access any non-register shader-specific PAL
// metadata key.
unsigned ScratchSizeKey = PALMD::Key::CS_SCRATCH_SIZE;
switch (MF.getFunction()->getCallingConv()) {
switch (MF.getFunction().getCallingConv()) {
case CallingConv::AMDGPU_PS:
ScratchSizeKey = PALMD::Key::PS_SCRATCH_SIZE;
break;
@ -1068,7 +1068,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
PALMD::Key::VS_NUM_USED_SGPRS - PALMD::Key::VS_SCRATCH_SIZE;
PALMetadataMap[NumUsedVgprsKey] = CurrentProgramInfo.NumVGPRsForWavesPerEU;
PALMetadataMap[NumUsedSgprsKey] = CurrentProgramInfo.NumSGPRsForWavesPerEU;
if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
PALMetadataMap[Rsrc1Reg] |= CurrentProgramInfo.ComputePGMRSrc1;
PALMetadataMap[Rsrc2Reg] |= CurrentProgramInfo.ComputePGMRSrc2;
// ScratchSize is in bytes, 16 aligned.
@ -1083,7 +1083,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
PALMetadataMap[ScratchSizeKey] |=
alignTo(CurrentProgramInfo.ScratchSize, 16);
}
if (MF.getFunction()->getCallingConv() == CallingConv::AMDGPU_PS) {
if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
PALMetadataMap[Rsrc2Reg] |=
S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks);
PALMetadataMap[R_0286CC_SPI_PS_INPUT_ENA / 4] |= MFI->getPSInputEnable();

4
llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
View File

@ -43,7 +43,7 @@ unsigned AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
MachineFunction &MF = MIRBuilder.getMF();
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
MachineRegisterInfo &MRI = MF.getRegInfo();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUASI.CONSTANT_ADDRESS);
LLT PtrType = getLLTForType(*PtrTy, DL);
@ -64,7 +64,7 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
Type *ParamTy, unsigned Offset,
unsigned DstReg) const {
MachineFunction &MF = MIRBuilder.getMF();
const Function &F = *MF.getFunction();
const Function &F = MF.getFunction();
const DataLayout &DL = F.getParent()->getDataLayout();
PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUASI.CONSTANT_ADDRESS);
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));

Some files were not shown because too many files have changed in this diff Show More