Add a TableGen CodeGenSubRegIndex class.
This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. llvm-svn: 149418
This commit is contained in:
Jakob Stoklund Olesen
parent
44091c2f10
commit
f1bb151917
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@ -21,6 +21,34 @@
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// CodeGenSubRegIndex
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//===----------------------------------------------------------------------===//
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CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum)
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: TheDef(R),
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EnumValue(Enum)
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{}
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std::string CodeGenSubRegIndex::getNamespace() const {
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if (TheDef->getValue("Namespace"))
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return TheDef->getValueAsString("Namespace");
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else
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return "";
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}
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const std::string &CodeGenSubRegIndex::getName() const {
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return TheDef->getName();
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}
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std::string CodeGenSubRegIndex::getQualifiedName() const {
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std::string N = getNamespace();
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if (!N.empty())
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N += "::";
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N += getName();
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return N;
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}
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//===----------------------------------------------------------------------===//
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// CodeGenRegister
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//===----------------------------------------------------------------------===//
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@ -40,8 +68,8 @@ const std::string &CodeGenRegister::getName() const {
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namespace {
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struct Orphan {
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CodeGenRegister *SubReg;
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Record *First, *Second;
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Orphan(CodeGenRegister *r, Record *a, Record *b)
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CodeGenSubRegIndex *First, *Second;
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Orphan(CodeGenRegister *r, CodeGenSubRegIndex *a, CodeGenSubRegIndex *b)
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: SubReg(r), First(a), Second(b) {}
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};
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}
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@ -62,8 +90,9 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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// First insert the direct subregs and make sure they are fully indexed.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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if (!SubRegs.insert(std::make_pair(Indices[i], SR)).second)
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throw TGError(TheDef->getLoc(), "SubRegIndex " + Indices[i]->getName() +
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CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(Indices[i]);
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if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
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throw TGError(TheDef->getLoc(), "SubRegIndex " + Idx->getName() +
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" appears twice in Register " + getName());
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}
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@ -74,6 +103,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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// Here the order is important - earlier subregs take precedence.
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for (unsigned i = 0, e = SubList.size(); i != e; ++i) {
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CodeGenRegister *SR = RegBank.getReg(SubList[i]);
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CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(Indices[i]);
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const SubRegMap &Map = SR->getSubRegs(RegBank);
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// Add this as a super-register of SR now all sub-registers are in the list.
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@ -84,7 +114,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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for (SubRegMap::const_iterator SI = Map.begin(), SE = Map.end(); SI != SE;
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++SI) {
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if (!SubRegs.insert(*SI).second)
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Orphans.push_back(Orphan(SI->second, Indices[i], SI->first));
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Orphans.push_back(Orphan(SI->second, Idx, SI->first));
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// Noop sub-register indexes are possible, so avoid duplicates.
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if (SI->second != SR)
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@ -104,6 +134,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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CodeGenSubRegIndex *BaseIdx = RegBank.getSubRegIdx(BaseIdxInit->getDef());
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// Resolve list of subreg indices into R2.
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CodeGenRegister *R2 = this;
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@ -113,8 +144,9 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
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throw TGError(TheDef->getLoc(), "Invalid SubClassIndex in " +
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Pat->getAsString());
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CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(IdxInit->getDef());
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const SubRegMap &R2Subs = R2->getSubRegs(RegBank);
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SubRegMap::const_iterator ni = R2Subs.find(IdxInit->getDef());
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SubRegMap::const_iterator ni = R2Subs.find(Idx);
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if (ni == R2Subs.end())
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throw TGError(TheDef->getLoc(), "Composite " + Pat->getAsString() +
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" refers to bad index in " + R2->getName());
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@ -122,7 +154,7 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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}
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// Insert composite index. Allow overriding inherited indices etc.
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SubRegs[BaseIdxInit->getDef()] = R2;
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SubRegs[BaseIdx] = R2;
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// R2 is no longer an orphan.
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for (unsigned j = 0, je = Orphans.size(); j != je; ++j)
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@ -143,13 +175,15 @@ CodeGenRegister::getSubRegs(CodeGenRegBank &RegBank) {
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}
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void
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CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const {
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CodeGenRegister::addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
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CodeGenRegBank &RegBank) const {
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assert(SubRegsComplete && "Must precompute sub-registers");
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std::vector<Record*> Indices = TheDef->getValueAsListOfDefs("SubRegIndices");
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for (unsigned i = 0, e = Indices.size(); i != e; ++i) {
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CodeGenRegister *SR = SubRegs.find(Indices[i])->second;
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CodeGenSubRegIndex *Idx = RegBank.getSubRegIdx(Indices[i]);
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CodeGenRegister *SR = SubRegs.find(Idx)->second;
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if (OSet.insert(SR))
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SR->addSubRegsPreOrder(OSet);
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SR->addSubRegsPreOrder(OSet, RegBank);
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}
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}
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@ -516,8 +550,10 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
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}
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void
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CodeGenRegisterClass::getSuperRegClasses(Record *SubIdx, BitVector &Out) const {
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DenseMap<Record*, SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
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CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx,
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BitVector &Out) const {
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DenseMap<CodeGenSubRegIndex*,
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SmallPtrSet<CodeGenRegisterClass*, 8> >::const_iterator
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FindI = SuperRegClasses.find(SubIdx);
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if (FindI == SuperRegClasses.end())
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return;
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@ -539,9 +575,11 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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// Read in the user-defined (named) sub-register indices.
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// More indices will be synthesized later.
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SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
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std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
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NumNamedIndices = SubRegIndices.size();
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std::vector<Record*> SRIs = Records.getAllDerivedDefinitions("SubRegIndex");
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std::sort(SRIs.begin(), SRIs.end(), LessRecord());
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NumNamedIndices = SRIs.size();
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for (unsigned i = 0, e = SRIs.size(); i != e; ++i)
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getSubRegIdx(SRIs[i]);
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// Read in the register definitions.
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std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
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@ -585,6 +623,15 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
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CodeGenRegisterClass::computeSubClasses(*this);
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}
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CodeGenSubRegIndex *CodeGenRegBank::getSubRegIdx(Record *Def) {
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CodeGenSubRegIndex *&Idx = Def2SubRegIdx[Def];
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if (Idx)
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return Idx;
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Idx = new CodeGenSubRegIndex(Def, SubRegIndices.size() + 1);
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SubRegIndices.push_back(Idx);
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return Idx;
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}
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CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
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CodeGenRegister *&Reg = Def2Reg[Def];
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if (Reg)
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@ -630,34 +677,28 @@ CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
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throw TGError(Def->getLoc(), "Not a known RegisterClass!");
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}
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Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B,
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bool create) {
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CodeGenSubRegIndex*
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CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A,
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CodeGenSubRegIndex *B,
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bool create) {
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// Look for an existing entry.
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Record *&Comp = Composite[std::make_pair(A, B)];
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CodeGenSubRegIndex *&Comp = Composite[std::make_pair(A, B)];
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if (Comp || !create)
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return Comp;
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// None exists, synthesize one.
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std::string Name = A->getName() + "_then_" + B->getName();
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Comp = new Record(Name, SMLoc(), Records);
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SubRegIndices.push_back(Comp);
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Comp = getSubRegIdx(new Record(Name, SMLoc(), Records));
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return Comp;
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}
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unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
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std::vector<Record*>::const_iterator i =
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std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
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assert(i != SubRegIndices.end() && "Not a SubRegIndex");
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return (i - SubRegIndices.begin()) + 1;
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}
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void CodeGenRegBank::computeComposites() {
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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CodeGenRegister *Reg1 = Registers[i];
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const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
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for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
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e1 = SRM1.end(); i1 != e1; ++i1) {
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Record *Idx1 = i1->first;
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CodeGenSubRegIndex *Idx1 = i1->first;
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CodeGenRegister *Reg2 = i1->second;
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// Ignore identity compositions.
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if (Reg1 == Reg2)
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@ -666,7 +707,8 @@ void CodeGenRegBank::computeComposites() {
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// Try composing Idx1 with another SubRegIndex.
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for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM2.begin(),
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e2 = SRM2.end(); i2 != e2; ++i2) {
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std::pair<Record*, Record*> IdxPair(Idx1, i2->first);
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std::pair<CodeGenSubRegIndex*, CodeGenSubRegIndex*>
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IdxPair(Idx1, i2->first);
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CodeGenRegister *Reg3 = i2->second;
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// Ignore identity compositions.
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if (Reg2 == Reg3)
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@ -679,11 +721,11 @@ void CodeGenRegBank::computeComposites() {
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Composite.insert(std::make_pair(IdxPair, i1d->first));
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// Conflicting composition? Emit a warning but allow it.
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if (!Ins.second && Ins.first->second != i1d->first) {
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errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
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<< " and " << getQualifiedName(IdxPair.second)
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errs() << "Warning: SubRegIndex " << Idx1->getQualifiedName()
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<< " and " << IdxPair.second->getQualifiedName()
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<< " compose ambiguously as "
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<< getQualifiedName(Ins.first->second) << " or "
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<< getQualifiedName(i1d->first) << "\n";
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<< Ins.first->second->getQualifiedName() << " or "
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<< i1d->first->getQualifiedName() << "\n";
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}
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}
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}
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@ -826,7 +868,8 @@ void CodeGenRegBank::inferCommonSubClass(CodeGenRegisterClass *RC) {
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//
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void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
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// Map SubRegIndex to set of registers in RC supporting that SubRegIndex.
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typedef std::map<Record*, CodeGenRegister::Set, LessRecord> SubReg2SetMap;
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typedef std::map<CodeGenSubRegIndex*, CodeGenRegister::Set,
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CodeGenSubRegIndex::Less> SubReg2SetMap;
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// Compute the set of registers supporting each SubRegIndex.
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SubReg2SetMap SRSets;
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@ -841,7 +884,7 @@ void CodeGenRegBank::inferSubClassWithSubReg(CodeGenRegisterClass *RC) {
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// Find matching classes for all SRSets entries. Iterate in SubRegIndex
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// numerical order to visit synthetic indices last.
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for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
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Record *SubIdx = SubRegIndices[sri];
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CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
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SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
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// Unsupported SubRegIndex. Skip it.
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if (I == SRSets.end())
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@ -873,7 +916,7 @@ void CodeGenRegBank::inferMatchingSuperRegClass(CodeGenRegisterClass *RC,
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// Iterate in SubRegIndex numerical order to visit synthetic indices last.
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for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
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Record *SubIdx = SubRegIndices[sri];
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CodeGenSubRegIndex *SubIdx = SubRegIndices[sri];
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// Skip indexes that aren't fully supported by RC's registers. This was
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// computed by inferSubClassWithSubReg() above which should have been
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// called first.
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@ -1010,7 +1053,7 @@ BitVector CodeGenRegBank::computeCoveredRegisters(ArrayRef<Record*> Regs) {
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if (Set.insert(Reg))
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// Reg is new, add all sub-registers.
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// The pre-ordering is not important here.
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Reg->addSubRegsPreOrder(Set);
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Reg->addSubRegsPreOrder(Set, *this);
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}
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// Second, find all super-registers that are completely covered by the set.
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@ -31,6 +31,28 @@
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namespace llvm {
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class CodeGenRegBank;
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/// CodeGenSubRegIndex - Represents a sub-register index.
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class CodeGenSubRegIndex {
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Record *const TheDef;
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const unsigned EnumValue;
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public:
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CodeGenSubRegIndex(Record *R, unsigned Enum);
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const std::string &getName() const;
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std::string getNamespace() const;
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std::string getQualifiedName() const;
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// Order CodeGenSubRegIndex pointers by EnumValue.
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struct Less {
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bool operator()(const CodeGenSubRegIndex *A,
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const CodeGenSubRegIndex *B) const {
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assert(A && B);
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return A->EnumValue < B->EnumValue;
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}
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};
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};
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/// CodeGenRegister - Represents a register definition.
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struct CodeGenRegister {
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Record *TheDef;
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@ -39,7 +61,8 @@ namespace llvm {
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bool CoveredBySubRegs;
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// Map SubRegIndex -> Register.
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typedef std::map<Record*, CodeGenRegister*, LessRecord> SubRegMap;
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typedef std::map<CodeGenSubRegIndex*, CodeGenRegister*,
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CodeGenSubRegIndex::Less> SubRegMap;
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CodeGenRegister(Record *R, unsigned Enum);
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@ -55,7 +78,8 @@ namespace llvm {
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}
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// Add sub-registers to OSet following a pre-order defined by the .td file.
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void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet) const;
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void addSubRegsPreOrder(SetVector<CodeGenRegister*> &OSet,
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CodeGenRegBank&) const;
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// List of super-registers in topological order, small to large.
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typedef std::vector<CodeGenRegister*> SuperRegList;
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@ -104,14 +128,15 @@ namespace llvm {
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// Map SubRegIndex -> sub-class. This is the largest sub-class where all
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// registers have a SubRegIndex sub-register.
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DenseMap<Record*, CodeGenRegisterClass*> SubClassWithSubReg;
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DenseMap<CodeGenSubRegIndex*, CodeGenRegisterClass*> SubClassWithSubReg;
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// Map SubRegIndex -> set of super-reg classes. This is all register
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// classes SuperRC such that:
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//
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// R:SubRegIndex in this RC for all R in SuperRC.
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//
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DenseMap<Record*, SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
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DenseMap<CodeGenSubRegIndex*,
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SmallPtrSet<CodeGenRegisterClass*, 8> > SuperRegClasses;
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public:
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unsigned EnumValue;
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std::string Namespace;
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@ -158,20 +183,23 @@ namespace llvm {
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// getSubClassWithSubReg - Returns the largest sub-class where all
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// registers have a SubIdx sub-register.
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CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const {
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CodeGenRegisterClass*
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getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
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return SubClassWithSubReg.lookup(SubIdx);
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}
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void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) {
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void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SubRC) {
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SubClassWithSubReg[SubIdx] = SubRC;
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}
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// getSuperRegClasses - Returns a bit vector of all register classes
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// containing only SubIdx super-registers of this class.
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void getSuperRegClasses(Record *SubIdx, BitVector &Out) const;
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void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
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// addSuperRegClass - Add a class containing only SudIdx super-registers.
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void addSuperRegClass(Record *SubIdx, CodeGenRegisterClass *SuperRC) {
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void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
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CodeGenRegisterClass *SuperRC) {
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SuperRegClasses[SubIdx].insert(SuperRC);
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}
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@ -240,8 +268,12 @@ namespace llvm {
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RecordKeeper &Records;
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SetTheory Sets;
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std::vector<Record*> SubRegIndices;
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// SubRegIndices.
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std::vector<CodeGenSubRegIndex*> SubRegIndices;
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DenseMap<Record*, CodeGenSubRegIndex*> Def2SubRegIdx;
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unsigned NumNamedIndices;
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// Registers.
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std::vector<CodeGenRegister*> Registers;
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DenseMap<Record*, CodeGenRegister*> Def2Reg;
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@ -268,7 +300,8 @@ namespace llvm {
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// Composite SubRegIndex instances.
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// Map (SubRegIndex, SubRegIndex) -> SubRegIndex.
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typedef DenseMap<std::pair<Record*, Record*>, Record*> CompositeMap;
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typedef DenseMap<std::pair<CodeGenSubRegIndex*, CodeGenSubRegIndex*>,
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CodeGenSubRegIndex*> CompositeMap;
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CompositeMap Composite;
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// Populate the Composite map from sub-register relationships.
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@ -282,14 +315,16 @@ namespace llvm {
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// Sub-register indices. The first NumNamedIndices are defined by the user
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// in the .td files. The rest are synthesized such that all sub-registers
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// have a unique name.
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||||
const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
|
||||
ArrayRef<CodeGenSubRegIndex*> getSubRegIndices() { return SubRegIndices; }
|
||||
unsigned getNumNamedIndices() { return NumNamedIndices; }
|
||||
|
||||
// Map a SubRegIndex Record to its enum value.
|
||||
unsigned getSubRegIndexNo(Record *idx);
|
||||
// Find a SubRegIndex form its Record def.
|
||||
CodeGenSubRegIndex *getSubRegIdx(Record*);
|
||||
|
||||
// Find or create a sub-register index representing the A+B composition.
|
||||
Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
|
||||
CodeGenSubRegIndex *getCompositeSubRegIndex(CodeGenSubRegIndex *A,
|
||||
CodeGenSubRegIndex *B,
|
||||
bool create = false);
|
||||
|
||||
const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
|
||||
|
||||
|
|
|
|||
|
|
@ -282,7 +282,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
continue;
|
||||
// getSubRegs() orders by SubRegIndex. We want a topological order.
|
||||
SetVector<CodeGenRegister*> SR;
|
||||
Reg.addSubRegsPreOrder(SR);
|
||||
Reg.addSubRegsPreOrder(SR, RegBank);
|
||||
OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
|
||||
for (unsigned j = 0, je = SR.size(); j != je; ++j)
|
||||
OS << getQualifiedName(SR[j]->TheDef) << ", ";
|
||||
|
|
@ -431,10 +431,11 @@ RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
|
|||
"unsigned) const;\n"
|
||||
<< "};\n\n";
|
||||
|
||||
const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
|
||||
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
|
||||
if (!SubRegIndices.empty()) {
|
||||
OS << "\n// Subregister indices\n";
|
||||
std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
|
||||
std::string Namespace =
|
||||
SubRegIndices[0]->getNamespace();
|
||||
if (!Namespace.empty())
|
||||
OS << "namespace " << Namespace << " {\n";
|
||||
OS << "enum {\n NoSubRegister,\n";
|
||||
|
|
@ -690,7 +691,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
unsigned NamedIndices = RegBank.getNumNamedIndices();
|
||||
|
||||
// Emit SubRegIndex names, skipping 0
|
||||
const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
|
||||
ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
|
||||
OS << "\n static const char *const " << TargetName
|
||||
<< "SubRegIndexTable[] = { \"";
|
||||
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
||||
|
|
@ -729,7 +730,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
OS << " default: return 0;\n";
|
||||
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
|
||||
ie = SRM.end(); ii != ie; ++ii)
|
||||
OS << " case " << getQualifiedName(ii->first)
|
||||
OS << " case " << ii->first->getQualifiedName()
|
||||
<< ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
|
||||
OS << " };\n" << " break;\n";
|
||||
}
|
||||
|
|
@ -749,7 +750,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
|
||||
ie = SRM.end(); ii != ie; ++ii)
|
||||
OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
|
||||
<< ") return " << getQualifiedName(ii->first) << ";\n";
|
||||
<< ") return " << ii->first->getQualifiedName() << ";\n";
|
||||
OS << " return 0;\n";
|
||||
}
|
||||
OS << " };\n";
|
||||
|
|
@ -764,15 +765,16 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
|
||||
bool Open = false;
|
||||
for (unsigned j = 0; j != e; ++j) {
|
||||
if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
|
||||
SubRegIndices[j])) {
|
||||
if (CodeGenSubRegIndex *Comp =
|
||||
RegBank.getCompositeSubRegIndex(SubRegIndices[i],
|
||||
SubRegIndices[j])) {
|
||||
if (!Open) {
|
||||
OS << " case " << getQualifiedName(SubRegIndices[i])
|
||||
OS << " case " << SubRegIndices[i]->getQualifiedName()
|
||||
<< ": switch(IdxB) {\n default: return IdxB;\n";
|
||||
Open = true;
|
||||
}
|
||||
OS << " case " << getQualifiedName(SubRegIndices[j])
|
||||
<< ": return " << getQualifiedName(Comp) << ";\n";
|
||||
OS << " case " << SubRegIndices[j]->getQualifiedName()
|
||||
<< ": return " << Comp->getQualifiedName() << ";\n";
|
||||
}
|
||||
}
|
||||
if (Open)
|
||||
|
|
@ -801,7 +803,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
|
||||
OS << " {\t// " << RC.getName() << "\n";
|
||||
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
||||
Record *Idx = SubRegIndices[sri];
|
||||
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
|
||||
if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
|
||||
OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
|
||||
<< " -> " << SRC->getName() << "\n";
|
||||
|
|
@ -842,7 +844,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
|
|||
const CodeGenRegisterClass &RC = *RegisterClasses[rci];
|
||||
OS << " {\t// " << RC.getName() << "\n";
|
||||
for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
|
||||
Record *Idx = SubRegIndices[sri];
|
||||
CodeGenSubRegIndex *Idx = SubRegIndices[sri];
|
||||
BV.reset();
|
||||
RC.getSuperRegClasses(Idx, BV);
|
||||
OS << " { ";
|
||||
|
|
|
|||
Loading…
Reference in New Issue