From f0b36a3cfd1ae7f5e85f7c217698e3001b60b313 Mon Sep 17 00:00:00 2001
From: Bill Wendling <isanbard@gmail.com>
Date: Fri, 3 Dec 2010 00:53:22 +0000
Subject: [PATCH] The tLDR instruction wasn't encoded properly:

<MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>>

Notice that the "reg" here is 0, which is an invalid register. Put a check in
the code for this to prevent crashing.

llvm-svn: 120766
---
 llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 4b059197ff05..d6926d9450ed 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -642,8 +642,12 @@ static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
   const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
   unsigned Rn = getARMRegisterNumbering(MO.getReg());
   unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
-  unsigned Rm = getARMRegisterNumbering(MO2.getReg());
-  return (Rm << 3) | (Imm5 << 3) | Rn;
+
+  if (MO2.getReg() != 0)
+    // Is an immediate.
+    Imm5 = getARMRegisterNumbering(MO2.getReg());
+
+  return (Imm5 << 3) | Rn;
 }
 
 /// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.