R600/SI: Unify VOP2 instructions which are VOP3-only on VI
This removes some duplicated classes and definitions. These instructions are defined: _e32 // pseudo _e32_si _e64 // pseudo _e64_si _e64_vi llvm-svn: 226191
This commit is contained in:
Marek Olsak
parent
c536850526
commit
f0b130ace0
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@ -36,6 +36,12 @@ class vop2 <bits<6> si, bits<6> vi = si> : vop {
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field bits<10> VI3 = {0, 1, 0, 0, vi{5-0}};
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}
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// Specify a VOP2 opcode for SI and VOP3 opcode for VI
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// that doesn't have VOP2 encoding on VI
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class vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
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let VI3 = vi;
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}
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class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
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let SI3 = si;
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let VI3 = vi;
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@ -848,6 +854,16 @@ class VOP2_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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let isPseudo = 1;
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}
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multiclass VOP2SI_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, string revOpSI> {
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def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
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VOP2_REV<revOpSI#"_e32", !eq(revOpSI, opName)>;
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def _si : VOP2 <op.SI, outs, ins, opName#asm, []>,
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VOP2_REV<revOpSI#"_e32_si", !eq(revOpSI, opName)>,
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SIMCInstr <opName#"_e32", SISubtarget.SI>;
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}
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multiclass VOP2_m <vop2 op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, string revOpSI, string revOpVI> {
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def "" : VOP2_Pseudo <outs, ins, pattern, opName>,
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@ -889,16 +905,6 @@ class VOP3_Real_vi <bits<10> op, dag outs, dag ins, string asm, string opName> :
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VOP3e_vi <op>,
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SIMCInstr <opName#"_e64", SISubtarget.VI>;
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// VI only instruction
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class VOP3_vi <bits<10> op, string opName, dag outs, dag ins, string asm,
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list<dag> pattern, int NumSrcArgs, bit HasMods = 1> :
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VOP3Common <outs, ins, asm, pattern>,
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VOP <opName>,
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VOP3e_vi <op>,
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VOP3DisableFields<!if(!eq(NumSrcArgs, 1), 0, 1),
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!if(!eq(NumSrcArgs, 2), 0, 1),
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HasMods>;
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multiclass VOP3_m <vop op, dag outs, dag ins, string asm, list<dag> pattern,
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string opName, int NumSrcArgs, bit HasMods = 1> {
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@ -1106,6 +1112,33 @@ multiclass VOP2bInst <vop2 op, string opName, VOPProfile P,
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revOp, P.HasModifiers
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>;
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// A VOP2 instruction that is VOP3-only on VI.
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multiclass VOP2_VI3_Helper <vop23 op, string opName, dag outs,
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dag ins32, string asm32, list<dag> pat32,
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dag ins64, string asm64, list<dag> pat64,
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string revOpSI, string revOpVI, bit HasMods> {
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defm _e32 : VOP2SI_m <op, outs, ins32, asm32, pat32, opName, revOpSI>;
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defm _e64 : VOP3_2_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName,
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revOpSI, revOpVI, HasMods>;
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}
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multiclass VOP2_VI3_Inst <vop23 op, string opName, VOPProfile P,
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SDPatternOperator node = null_frag,
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string revOpSI = opName, string revOpVI = revOpSI>
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: VOP2_VI3_Helper <
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op, opName, P.Outs,
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P.Ins32, P.Asm32, [],
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P.Ins64, P.Asm64,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))]),
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revOpSI, revOpVI, P.HasModifiers
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>;
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class VOPC_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
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VOPCCommon <ins, "", pattern>,
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VOP <opName>,
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@ -1241,34 +1274,6 @@ multiclass VOP3Inst <vop3 op, string opName, VOPProfile P,
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P.NumSrcArgs, P.HasModifiers
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>;
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class VOP3InstVI <bits<10> op, string opName, VOPProfile P,
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SDPatternOperator node = null_frag> : VOP3_vi <
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op, opName#"_vi", P.Outs, P.Ins64, opName#P.Asm64,
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!if(!eq(P.NumSrcArgs, 3),
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1,
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P.Src2VT:$src2))]),
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!if(!eq(P.NumSrcArgs, 2),
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod)),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0, P.Src1VT:$src1))])
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/* P.NumSrcArgs == 1 */,
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!if(P.HasModifiers,
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[(set P.DstVT:$dst,
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(node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers,
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i1:$clamp, i32:$omod))))],
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[(set P.DstVT:$dst, (node P.Src0VT:$src0))]))),
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P.NumSrcArgs, P.HasModifiers
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>;
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multiclass VOP3b_Helper <vop op, RegisterClass vrc, RegisterOperand arc,
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string opName, list<dag> pattern> :
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VOP3b_2_m <
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@ -1568,30 +1568,33 @@ defm V_LSHL_B32 : VOP2Inst <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32, shl>;
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}
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} // End isCommutable = 1
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} // End let SubtargetPredicate = SICI
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defm V_BFM_B32 : VOP2Inst <vop2<0x1e>, "v_bfm_b32", VOP_I32_I32_I32,
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AMDGPUbfm>;
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defm V_BCNT_U32_B32 : VOP2Inst <vop2<0x22>, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
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defm V_MBCNT_LO_U32_B32 : VOP2Inst <vop2<0x23>, "v_mbcnt_lo_u32_b32",
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defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", VOP_I32_I32_I32,
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AMDGPUbfm
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>;
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defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32",
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VOP_I32_I32_I32
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>;
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defm V_MBCNT_HI_U32_B32 : VOP2Inst <vop2<0x24>, "v_mbcnt_hi_u32_b32",
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defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32",
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VOP_I32_I32_I32
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>;
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defm V_LDEXP_F32 : VOP2Inst <vop2<0x2b>, "v_ldexp_f32",
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defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32",
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VOP_I32_I32_I32
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>;
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defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32",
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VOP_F32_F32_I32, AMDGPUldexp
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>;
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////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "v_cvt_pkaccum_u8_f32", []>;
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////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "v_cvt_pknorm_i16_f32", []>;
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////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "v_cvt_pknorm_u16_f32", []>;
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defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <vop2<0x2f>, "v_cvt_pkrtz_f16_f32",
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defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32",
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VOP_I32_F32_F32, int_SI_packf16
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>;
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////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "v_cvt_pk_u16_u32", []>;
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////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "v_cvt_pk_i16_i32", []>;
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} // End let SubtargetPredicate = SICI
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//===----------------------------------------------------------------------===//
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// VOP3 Instructions
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//===----------------------------------------------------------------------===//
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@ -2731,16 +2734,12 @@ def : Pat <
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(V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0))))
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>;
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let Predicates = [isSICI] in {
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def : Pat <
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(int_SI_tid),
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(V_MBCNT_HI_U32_B32_e64 0xffffffff,
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(V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
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>;
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}
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//===----------------------------------------------------------------------===//
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// VOP3 Patterns
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//===----------------------------------------------------------------------===//
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@ -11,22 +11,6 @@
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let SubtargetPredicate = isVI in {
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def V_LDEXP_F32 : VOP3InstVI <0x288, "v_ldexp_f32", VOP_F32_F32_I32,
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AMDGPUldexp
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>;
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def V_BFM_B32 : VOP3InstVI <0x293, "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>;
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def V_BCNT_U32_B32 : VOP3InstVI <0x28b, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
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def V_MBCNT_LO_U32_B32 : VOP3InstVI <0x28c, "v_mbcnt_lo_u32_b32",
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VOP_I32_I32_I32
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>;
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def V_MBCNT_HI_U32_B32 : VOP3InstVI <0x28d, "v_mbcnt_hi_u32_b32",
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VOP_I32_I32_I32
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>;
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def V_CVT_PKRTZ_F16_F32 : VOP3InstVI <0x296, "v_cvt_pkrtz_f16_f32",
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VOP_I32_F32_F32, int_SI_packf16
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>;
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defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi <
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0x14, "buffer_load_dword", VGPR_32, i32, global_load
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>;
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@ -37,22 +21,13 @@ defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi <
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} // End SubtargetPredicate = isVI
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//===----------------------------------------------------------------------===//
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// VOP2 Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [isVI] in {
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def : Pat <
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(int_SI_tid),
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(V_MBCNT_HI_U32_B32 0xffffffff,
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(V_MBCNT_LO_U32_B32 0xffffffff, 0))
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>;
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//===----------------------------------------------------------------------===//
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// SMEM Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [isVI] in {
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// 1. Offset as 8bit DWORD immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, IMM20bit:$offset),
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