This patch fixes 8 out of 20 unexpected failures in "make check"
when run on an Intel Atom processor. The failures have arisen due to changes elsewhere in the trunk over the past 8 weeks or so. These failures were not detected by the Atom buildbot because the CPU on the Atom buildbot was not being detected as an Atom CPU. The fix for this problem is in Host.cpp and X86Subtarget.cpp, but shall remain commented out until the current set of Atom test failures are fixed. Patch by Andy Zhang and Tyler Nowicki! llvm-svn: 160451
This commit is contained in:
Preston Gurd
parent
5e0c5e8108
commit
f0a48ec8f1
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@ -249,6 +249,9 @@ std::string sys::getHostCPUName() {
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case 28: // Most 45 nm Intel Atom processors
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case 38: // 45 nm Atom Lincroft
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case 39: // 32 nm Atom Medfield
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// re-enable when buildbot will pass all atom tests
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//case 53: // 32 nm Atom Midview
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//case 54: // 32 nm Atom Midview
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return "atom";
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default: return (Em64T) ? "x86-64" : "i686";
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@ -254,7 +254,8 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
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// Set processor type. Currently only Atom is detected.
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if (Family == 6 &&
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(Model == 28 || Model == 38 || Model == 39)) {
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(Model == 28 || Model == 38 || Model == 39
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/*|| Model == 53 || Model == 54*/)) {
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X86ProcFamily = IntelAtom;
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UseLeaForSP = true;
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@ -1,15 +1,15 @@
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; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=atom %s
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; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck -check-prefix=ATOM %s
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; RUN: llc < %s -mcpu=core2 -mtriple=i686-linux | FileCheck %s
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declare void @use_arr(i8*)
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declare void @many_params(i32, i32, i32, i32, i32, i32)
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define void @test1() nounwind {
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; atom: test1:
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; atom: leal -1052(%esp), %esp
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; atom-NOT: sub
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; atom: call
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; atom: leal 1052(%esp), %esp
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; ATOM: test1:
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; ATOM: leal -1052(%esp), %esp
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; ATOM-NOT: sub
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; ATOM: call
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; ATOM: leal 1052(%esp), %esp
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; CHECK: test1:
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; CHECK: subl
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@ -22,10 +22,10 @@ define void @test1() nounwind {
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}
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define void @test2() nounwind {
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; atom: test2:
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; atom: leal -28(%esp), %esp
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; atom: call
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; atom: leal 28(%esp), %esp
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; ATOM: test2:
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; ATOM: leal -28(%esp), %esp
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; ATOM: call
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; ATOM: leal 28(%esp), %esp
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; CHECK: test2:
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; CHECK-NOT: lea
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@ -34,9 +34,9 @@ define void @test2() nounwind {
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}
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define void @test3() nounwind {
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; atom: test3:
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; atom: leal -8(%esp), %esp
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; atom: leal 8(%esp), %esp
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; ATOM: test3:
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; ATOM: leal -8(%esp), %esp
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; ATOM: leal 8(%esp), %esp
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; CHECK: test3:
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; CHECK-NOT: lea
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@ -1,9 +1,17 @@
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; RUN: llc < %s -march=x86 >%t
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; RUN: grep "addl \$4," %t | count 3
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; RUN: not grep ",%" %t
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; RUN: llc < %s -march=x86 -mcpu=generic | FileCheck %s
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; RUN: llc < %s -march=x86 -mcpu=atom | FileCheck -check-prefix=ATOM %s
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define void @foo(float* nocapture %A, float* nocapture %B, float* nocapture %C, i32 %N) nounwind {
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; ATOM: foo
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; ATOM: addl
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; ATOM: leal
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; ATOM: leal
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; CHECK: foo
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; CHECK: addl
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; CHECK: addl
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; CEHCK: addl
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entry:
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%0 = icmp sgt i32 %N, 0 ; <i1> [#uses=1]
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br i1 %0, label %bb, label %return
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@ -1,6 +1,7 @@
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; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast -optimize-regalloc=0 | FileCheck %s
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; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
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; CHECKed instructions should be the same with or without -O0.
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; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=generic -regalloc=fast -optimize-regalloc=0 | FileCheck %s
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; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=generic -regalloc=fast | FileCheck %s
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; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -mcpu=atom -regalloc=fast -optimize-regalloc=0 | FileCheck -check-prefix=ATOM %s
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; CHECKed instructions should be the same with or without -O0 except on Intel Atom due to instruction scheduling.
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@.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
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@ -15,6 +16,19 @@ entry:
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; CHECK: movl %ebx, 40(%esp)
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; CHECK-NOT: movl
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; CHECK: addl %ebx, %eax
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; On Intel Atom the scheduler moves a movl instruction
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; used for the printf call to follow movl 24(%esp), %eax
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; ATOM: movl 24(%esp), %eax
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; ATOM: movl
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; ATOM: movl %eax, 36(%esp)
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; ATOM-NOT: movl
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; ATOM: movl 28(%esp), %ebx
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; ATOM-NOT: movl
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; ATOM: movl %ebx, 40(%esp)
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; ATOM-NOT: movl
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; ATOM: addl %ebx, %eax
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%retval = alloca i32 ; <i32*> [#uses=2]
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%"%ebx" = alloca i32 ; <i32*> [#uses=1]
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%"%eax" = alloca i32 ; <i32*> [#uses=2]
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@ -1,9 +1,16 @@
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; RUN: llc -march=x86 -mattr=+sse < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=generic -mattr=+sse < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=atom -mattr=+sse < %s | FileCheck -check-prefix=ATOM %s
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%vec = type <6 x float>
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; CHECK: divss
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; CHECK: divss
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; CHECK: divps
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; Scheduler causes a different instruction order to be produced on Intel Atom
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; ATOM: divps
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; ATOM: divss
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; ATOM: divss
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define %vec @vecdiv( %vec %p1, %vec %p2)
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{
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%result = fdiv %vec %p1, %p2
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@ -16,7 +16,7 @@ define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
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entry:
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; CHECK: shift1b:
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; CHECK: movd
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; CHECK-NEXT: psllq
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; CHECK: psllq
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%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
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%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
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%shl = shl <2 x i64> %val, %1
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@ -38,7 +38,7 @@ define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift2b:
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; CHECK: movd
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; CHECK-NEXT: pslld
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; CHECK: pslld
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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@ -16,7 +16,7 @@ define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
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entry:
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; CHECK: shift1b:
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; CHECK: movd
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; CHECK-NEXT: psrlq
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; CHECK: psrlq
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%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
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%1 = insertelement <2 x i64> %0, i64 %amt, i32 1
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%lshr = lshr <2 x i64> %val, %1
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@ -37,7 +37,7 @@ define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift2b:
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; CHECK: movd
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; CHECK-NEXT: psrld
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; CHECK: psrld
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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@ -63,7 +63,7 @@ entry:
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; CHECK: shift3b:
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; CHECK: movzwl
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; CHECK: movd
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; CHECK-NEXT: psrlw
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; CHECK: psrlw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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@ -28,7 +28,7 @@ define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift2b:
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; CHECK: movd
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; CHECK-NEXT: psrad
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; CHECK: psrad
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%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%1 = insertelement <4 x i32> %0, i32 %amt, i32 1
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%2 = insertelement <4 x i32> %1, i32 %amt, i32 2
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@ -52,7 +52,7 @@ entry:
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; CHECK: shift3b:
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; CHECK: movzwl
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; CHECK: movd
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; CHECK-NEXT: psraw
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; CHECK: psraw
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%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
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%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
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%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
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@ -6,7 +6,7 @@ define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5a:
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; CHECK: movd
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; CHECK-NEXT: pslld
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; CHECK: pslld
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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@ -20,7 +20,7 @@ define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
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entry:
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; CHECK: shift5b:
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; CHECK: movd
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; CHECK-NEXT: psrad
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; CHECK: psrad
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%amt = load i32* %pamt
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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@ -34,7 +34,7 @@ define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift5c:
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; CHECK: movd
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; CHECK-NEXT: pslld
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; CHECK: pslld
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shl = shl <4 x i32> %val, %shamt
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@ -47,7 +47,7 @@ define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
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entry:
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; CHECK: shift5d:
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; CHECK: movd
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; CHECK-NEXT: psrad
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; CHECK: psrad
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%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
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%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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%shr = ashr <4 x i32> %val, %shamt
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@ -1,8 +1,15 @@
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; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=generic -mattr=+sse42 < %s | FileCheck %s
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; RUN: llc -march=x86 -mcpu=atom -mattr=+sse42 < %s | FileCheck -check-prefix=ATOM %s
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; CHECK: paddd
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; CHECK: movl
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; CHECK: movlpd
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; Scheduler causes produce a different instruction order
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; ATOM: movl
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; ATOM: paddd
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; ATOM: movlpd
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; bitcast a v4i16 to v2i32
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define void @convert(<2 x i32>* %dst, <4 x i16>* %src) nounwind {
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