Simplify the coalescer (finally!) by making LiveIntervals::processImplicitDefs a little more aggressive and teaching liveintervals to make use of isUndef marker on MachineOperands.
llvm-svn: 76223
This commit is contained in:
Evan Cheng
parent
97190a2c93
commit
f08b003bf0
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@ -123,7 +123,6 @@ void LiveIntervals::processImplicitDefs() {
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++I;
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if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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unsigned Reg = MI->getOperand(0).getReg();
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MI->getOperand(0).setIsUndef();
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ImpDefRegs.insert(Reg);
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ImpDefMIs.push_back(MI);
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continue;
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@ -175,11 +174,13 @@ void LiveIntervals::processImplicitDefs() {
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for (unsigned i = 0, e = ImpDefMIs.size(); i != e; ++i) {
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MachineInstr *MI = ImpDefMIs[i];
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unsigned Reg = MI->getOperand(0).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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// Physical registers are not liveout (yet).
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continue;
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if (!ImpDefRegs.count(Reg))
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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!ImpDefRegs.count(Reg)) {
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// Delete all "local" implicit_def's. That include those which define
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// physical registers since they cannot be liveout.
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MI->eraseFromParent();
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continue;
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}
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// If there are multiple defs of the same register and at least one
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// is not an implicit_def, do not insert implicit_def's before the
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@ -195,6 +196,10 @@ void LiveIntervals::processImplicitDefs() {
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if (Skip)
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continue;
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// The only implicit_def which we want to keep are those that are live
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// out of its block.
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MI->eraseFromParent();
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for (MachineRegisterInfo::use_iterator UI = mri_->use_begin(Reg),
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UE = mri_->use_end(); UI != UE; ) {
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MachineOperand &RMO = UI.getOperand();
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@ -203,12 +208,19 @@ void LiveIntervals::processImplicitDefs() {
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MachineBasicBlock *RMBB = RMI->getParent();
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if (RMBB == MBB)
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continue;
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// Turn a copy use into an implicit_def.
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unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
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if (tii_->isMoveInstr(*RMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
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Reg == SrcReg) {
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RMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
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for (int j = RMI->getNumOperands() - 1, ee = 0; j > ee; --j)
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RMI->RemoveOperand(j);
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continue;
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}
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const TargetRegisterClass* RC = mri_->getRegClass(Reg);
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unsigned NewVReg = mri_->createVirtualRegister(RC);
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MachineInstrBuilder MIB =
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BuildMI(*RMBB, RMI, RMI->getDebugLoc(),
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tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg);
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(*MIB).getOperand(0).setIsUndef();
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RMO.setReg(NewVReg);
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RMO.setIsUndef();
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RMO.setIsKill();
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@ -593,17 +605,12 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
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unsigned MOIdx,
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LiveInterval &interval) {
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DOUT << "\t\tregister: "; DEBUG(printRegName(interval.reg));
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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if (mi->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
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DOUT << "is a implicit_def\n";
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return;
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}
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// Virtual registers may be defined multiple times (due to phi
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// elimination and 2-addr elimination). Much of what we do only has to be
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// done once for the vreg. We use an empty interval to detect the first
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// time we see a vreg.
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LiveVariables::VarInfo& vi = lv_->getVarInfo(interval.reg);
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if (interval.empty()) {
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// Get the Idx of the defining instructions.
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unsigned defIndex = getDefIndex(MIIdx);
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@ -982,6 +989,7 @@ void LiveIntervals::computeIntervals() {
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<< "********** Function: "
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<< ((Value*)mf_->getFunction())->getName() << '\n';
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SmallVector<unsigned, 8> UndefUses;
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for (MachineFunction::iterator MBBI = mf_->begin(), E = mf_->end();
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MBBI != E; ++MBBI) {
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MachineBasicBlock *MBB = MBBI;
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@ -1013,10 +1021,14 @@ void LiveIntervals::computeIntervals() {
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// Handle defs.
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for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.getReg())
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continue;
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// handle register defs - build intervals
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if (MO.isReg() && MO.getReg() && MO.isDef()) {
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if (MO.isDef())
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handleRegisterDef(MBB, MI, MIIndex, MO, i);
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}
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else if (MO.isUndef())
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UndefUses.push_back(MO.getReg());
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}
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// Skip over the empty slots after each instruction.
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@ -1031,6 +1043,14 @@ void LiveIntervals::computeIntervals() {
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MIIndex += InstrSlots::NUM;
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}
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}
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// Create empty intervals for registers defined by implicit_def's (except
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// for those implicit_def that define values which are liveout of their
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// blocks.
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for (unsigned i = 0, e = UndefUses.size(); i != e; ++i) {
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unsigned UndefReg = UndefUses[i];
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(void)getOrCreateInterval(UndefReg);
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}
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}
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bool LiveIntervals::findLiveInMBBs(unsigned Start, unsigned End,
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@ -1523,22 +1543,12 @@ rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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continue;
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if (RegJ == RegI) {
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Ops.push_back(j);
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if (!MOj.isUndef()) {
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HasUse |= MOj.isUse();
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HasDef |= MOj.isDef();
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}
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}
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if (HasUse && !li.liveAt(getUseIndex(index)))
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// Must be defined by an implicit def. It should not be spilled. Note,
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// this is for correctness reason. e.g.
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// 8 %reg1024<def> = IMPLICIT_DEF
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// 12 %reg1024<def> = INSERT_SUBREG %reg1024<kill>, %reg1025, 2
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// The live range [12, 14) are not part of the r1024 live interval since
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// it's defined by an implicit def. It will not conflicts with live
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// interval of r1025. Now suppose both registers are spilled, you can
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// easily see a situation where both registers are reloaded before
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// the INSERT_SUBREG and both target registers that would overlap.
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HasUse = false;
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}
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// Create a new virtual register for the spill interval.
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// Create the new register now so we can map the fold instruction
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@ -1728,7 +1738,8 @@ rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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unsigned index = getInstructionIndex(MI);
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if (index < start || index >= end)
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continue;
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if (O.isUse() && !li.liveAt(getUseIndex(index)))
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if (O.isUndef())
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// Must be defined by an implicit def. It should not be spilled. Note,
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// this is for correctness reason. e.g.
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// 8 %reg1024<def> = IMPLICIT_DEF
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@ -786,35 +786,6 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg,
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}
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}
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/// RemoveDeadImpDef - Remove implicit_def instructions which are "re-defining"
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/// registers due to insert_subreg coalescing. e.g.
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/// r1024 = op
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/// r1025 = implicit_def
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/// r1025 = insert_subreg r1025, r1024
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/// = op r1025
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/// =>
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/// r1025 = op
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/// r1025 = implicit_def
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/// r1025 = insert_subreg r1025, r1025
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/// = op r1025
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void
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SimpleRegisterCoalescing::RemoveDeadImpDef(unsigned Reg, LiveInterval &LI) {
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for (MachineRegisterInfo::reg_iterator I = mri_->reg_begin(Reg),
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E = mri_->reg_end(); I != E; ) {
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MachineOperand &O = I.getOperand();
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MachineInstr *DefMI = &*I;
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++I;
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if (!O.isDef())
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continue;
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if (DefMI->getOpcode() != TargetInstrInfo::IMPLICIT_DEF)
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continue;
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if (!LI.liveBeforeAndAt(li_->getInstructionIndex(DefMI)))
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continue;
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li_->RemoveMachineInstrFromMaps(DefMI);
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DefMI->eraseFromParent();
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}
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}
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/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
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/// due to live range lengthening as the result of coalescing.
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void SimpleRegisterCoalescing::RemoveUnnecessaryKills(unsigned Reg,
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@ -1002,65 +973,6 @@ bool SimpleRegisterCoalescing::CanCoalesceWithImpDef(MachineInstr *CopyMI,
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}
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/// TurnCopiesFromValNoToImpDefs - The specified value# is defined by an
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/// implicit_def and it is being removed. Turn all copies from this value#
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/// into implicit_defs.
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void SimpleRegisterCoalescing::TurnCopiesFromValNoToImpDefs(LiveInterval &li,
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VNInfo *VNI) {
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SmallVector<MachineInstr*, 4> ImpDefs;
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MachineOperand *LastUse = NULL;
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unsigned LastUseIdx = li_->getUseIndex(VNI->def);
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for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(li.reg),
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RE = mri_->reg_end(); RI != RE;) {
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MachineOperand *MO = &RI.getOperand();
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MachineInstr *MI = &*RI;
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++RI;
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if (MO->isDef()) {
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if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
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ImpDefs.push_back(MI);
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continue;
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}
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if (JoinedCopies.count(MI))
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continue;
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unsigned UseIdx = li_->getUseIndex(li_->getInstructionIndex(MI));
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LiveInterval::iterator ULR = li.FindLiveRangeContaining(UseIdx);
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if (ULR == li.end() || ULR->valno != VNI)
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continue;
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// If the use is a copy, turn it into an identity copy.
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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SrcReg == li.reg) {
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// Change it to an implicit_def.
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MI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
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for (int i = MI->getNumOperands() - 1, e = 0; i > e; --i)
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MI->RemoveOperand(i);
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// It's no longer a copy, update the valno it defines.
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unsigned DefIdx = li_->getDefIndex(UseIdx);
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LiveInterval &DstInt = li_->getInterval(DstReg);
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LiveInterval::iterator DLR = DstInt.FindLiveRangeContaining(DefIdx);
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assert(DLR != DstInt.end() && "Live range not found!");
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assert(DLR->valno->copy == MI);
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DLR->valno->copy = NULL;
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ReMatCopies.insert(MI);
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} else if (UseIdx > LastUseIdx) {
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LastUseIdx = UseIdx;
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LastUse = MO;
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}
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}
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if (LastUse) {
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LastUse->setIsKill();
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li.addKill(VNI, LastUseIdx+1, false);
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} else {
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// Remove dead implicit_def's.
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while (!ImpDefs.empty()) {
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MachineInstr *ImpDef = ImpDefs.back();
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ImpDefs.pop_back();
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li_->RemoveMachineInstrFromMaps(ImpDef);
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ImpDef->eraseFromParent();
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}
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}
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}
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/// isWinToJoinVRWithSrcPhysReg - Return true if it's worth while to join a
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/// a virtual destination register with physical source register.
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bool
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@ -1786,13 +1698,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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if (TargetRegisterInfo::isVirtualRegister(DstReg))
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RemoveUnnecessaryKills(DstReg, *ResDstInt);
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if (isInsSubReg)
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// Avoid:
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// r1024 = op
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// r1024 = implicit_def
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// ...
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// = r1024
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RemoveDeadImpDef(DstReg, *ResDstInt);
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UpdateRegDefsUses(SrcReg, DstReg, SubIdx);
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// SrcReg is guarateed to be the register whose live interval that is
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@ -1808,29 +1713,6 @@ bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
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delete SavedLI;
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}
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if (isEmpty) {
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// Now the copy is being coalesced away, the val# previously defined
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// by the copy is being defined by an IMPLICIT_DEF which defines a zero
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// length interval. Remove the val#.
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unsigned CopyIdx = li_->getDefIndex(li_->getInstructionIndex(CopyMI));
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const LiveRange *LR = ResDstInt->getLiveRangeContaining(CopyIdx);
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VNInfo *ImpVal = LR->valno;
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assert(ImpVal->def == CopyIdx);
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unsigned NextDef = LR->end;
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TurnCopiesFromValNoToImpDefs(*ResDstInt, ImpVal);
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ResDstInt->removeValNo(ImpVal);
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LR = ResDstInt->FindLiveRangeContaining(NextDef);
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if (LR != ResDstInt->end() && LR->valno->def == NextDef) {
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// Special case: vr1024 = implicit_def
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// vr1024 = insert_subreg vr1024, vr1025, c
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// The insert_subreg becomes a "copy" that defines a val# which can itself
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// be coalesced away.
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MachineInstr *DefMI = li_->getInstructionFromIndex(NextDef);
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if (DefMI->getOpcode() == TargetInstrInfo::INSERT_SUBREG)
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LR->valno->copy = DefMI;
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}
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}
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// If resulting interval has a preference that no longer fits because of subreg
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// coalescing, just clear the preference.
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unsigned Preference = getRegAllocPreference(ResDstInt->reg, *mf_, mri_, tri_);
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@ -2695,10 +2577,8 @@ SimpleRegisterCoalescing::TurnCopyIntoImpDef(MachineBasicBlock::iterator &I,
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if (EndMBB != MBB)
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return false;
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DstInt.removeValNo(DstLR->valno);
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CopyMI->setDesc(tii_->get(TargetInstrInfo::IMPLICIT_DEF));
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for (int i = CopyMI->getNumOperands() - 1, e = 0; i > e; --i)
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CopyMI->RemoveOperand(i);
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CopyMI->getOperand(0).setIsUndef();
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li_->RemoveMachineInstrFromMaps(CopyMI);
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CopyMI->eraseFromParent();
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bool NoUse = mri_->use_empty(SrcReg);
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if (NoUse) {
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for (MachineRegisterInfo::reg_iterator RI = mri_->reg_begin(SrcReg),
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@ -277,10 +277,6 @@ namespace llvm {
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/// subregister.
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void UpdateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
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/// RemoveDeadImpDef - Remove implicit_def instructions which are
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/// "re-defining" registers due to insert_subreg coalescing. e.g.
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void RemoveDeadImpDef(unsigned Reg, LiveInterval &LI);
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/// RemoveUnnecessaryKills - Remove kill markers that are no longer accurate
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/// due to live range lengthening as the result of coalescing.
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void RemoveUnnecessaryKills(unsigned Reg, LiveInterval &LI);
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