replica
/
hanchenye-llvm-project
2
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

Thumb2 two-operand 'mul' instruction wide encoding parsing. 

rdar://10449724

llvm-svn: 144684
This commit is contained in:
Jim Grosbach 2011-11-15 19:55:16 +00:00
parent 0ac9058f89
commit efa7e95d06
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/lib/Target/ARM/ARMInstrThumb2.td
View File

@ -4084,3 +4084,8 @@ def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
// for isel.
def : t2InstAlias<"mov${p} $Rd, $imm",
(t2MVNi rGPR:$Rd, t2_so_imm_not:$imm, pred:$p, zero_reg)>;
// Wide 'mul' encoding can be specified with only two operands.
def : t2InstAlias<"mul${p} $Rn, $Rm",
(t2MUL rGPR:$Rn, rGPR:$Rn, rGPR:$Rm, pred:$p)>;

14
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
View File

@ -4106,6 +4106,20 @@ bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
static_cast<ARMOperand*>(Operands[4])->getReg())))
return true;
// Also check the 'mul' syntax variant that doesn't specify an explicit
// destination register.
if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
static_cast<ARMOperand*>(Operands[3])->isReg() &&
static_cast<ARMOperand*>(Operands[4])->isReg() &&
// If the registers aren't low regs or the cc_out operand is zero
// outside of an IT block, we have to use the 32-bit encoding, so
// remove the cc_out operand.
(!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
!isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
!inITBlock()))
return true;
// Register-register 'add/sub' for thumb does not have a cc_out operand