[X86] Simplify ISD::LOAD handling in ReplaceNodeResults and ISD::STORE handling in LowerStore now that v2i32 is widened to v4i32.
llvm-svn: 368390
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@ -21396,14 +21396,13 @@ static SDValue LowerStore(SDValue Op, const X86Subtarget &Subtarget,
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return SDValue();
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}
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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assert(StoreVT.isVector() && StoreVT.getSizeInBits() == 64 &&
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"Unexpected VT");
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if (DAG.getTargetLoweringInfo().getTypeAction(*DAG.getContext(), StoreVT) !=
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TargetLowering::TypeWidenVector)
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return SDValue();
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assert(TLI.getTypeAction(*DAG.getContext(), StoreVT) ==
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TargetLowering::TypeWidenVector && "Unexpected type action!");
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MVT WideVT = MVT::getVectorVT(StoreVT.getVectorElementType(),
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StoreVT.getVectorNumElements() * 2);
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EVT WideVT = TLI.getTypeToTransformTo(*DAG.getContext(), StoreVT);
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StoredVal = DAG.getNode(ISD::CONCAT_VECTORS, dl, WideVT, StoredVal,
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DAG.getUNDEF(StoreVT));
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@ -28123,8 +28122,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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// cast since type legalization will try to use an i64 load.
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MVT VT = N->getSimpleValueType(0);
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assert(VT.isVector() && VT.getSizeInBits() == 64 && "Unexpected VT");
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if (getTypeAction(*DAG.getContext(), VT) != TypeWidenVector)
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return;
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assert(getTypeAction(*DAG.getContext(), VT) == TypeWidenVector &&
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"Unexpected type action!");
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if (!ISD::isNON_EXTLoad(N))
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return;
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auto *Ld = cast<LoadSDNode>(N);
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@ -28134,11 +28133,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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Ld->getPointerInfo(), Ld->getAlignment(),
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Ld->getMemOperand()->getFlags());
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SDValue Chain = Res.getValue(1);
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MVT WideVT = MVT::getVectorVT(LdVT, 2);
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Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, WideVT, Res);
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MVT CastVT = MVT::getVectorVT(VT.getVectorElementType(),
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VT.getVectorNumElements() * 2);
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Res = DAG.getBitcast(CastVT, Res);
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MVT VecVT = MVT::getVectorVT(LdVT, 2);
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Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Res);
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EVT WideVT = getTypeToTransformTo(*DAG.getContext(), VT);
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Res = DAG.getBitcast(WideVT, Res);
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Results.push_back(Res);
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Results.push_back(Chain);
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return;
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