AMDGPU/SI: Don't fix a PHI under uniform branch in SIFixSGPRCopies only when sources and destination are all sgprs

Summary:
  If a PHI has at lease one VGPR operand, we have to fix the PHI
in SIFixSGPRCopies.

Reviewer:
  Matt

Differential Revision:
  http://reviews.llvm.org/D34727

llvm-svn: 309959
This commit is contained in:
Changpeng Fang 2017-08-03 16:37:02 +00:00
parent 6c2ded879d
commit ef4dbb46da
2 changed files with 25 additions and 3 deletions

View File

@ -604,7 +604,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
// We don't need to fix the PHI if the common dominator of the
// two incoming blocks terminates with a uniform branch.
if (MI.getNumExplicitOperands() == 5) {
bool HasVGPROperand = phiHasVGPROperands(MI, MRI, TRI, TII);
if (MI.getNumExplicitOperands() == 5 && !HasVGPROperand) {
MachineBasicBlock *MBB0 = MI.getOperand(2).getMBB();
MachineBasicBlock *MBB1 = MI.getOperand(4).getMBB();
@ -649,8 +650,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
// is no chance for values to be over-written.
SmallSet<unsigned, 8> Visited;
if (phiHasVGPROperands(MI, MRI, TRI, TII) ||
!phiHasBreakDef(MI, MRI, Visited)) {
if (HasVGPROperand || !phiHasBreakDef(MI, MRI, Visited)) {
DEBUG(dbgs() << "Fixing PHI: " << MI);
TII->moveToVALU(MI);
}

View File

@ -557,6 +557,28 @@ done:
ret void
}
; GCN-LABEL: {{^}}move_to_valu_vgpr_operand_phi:
; GCN: v_add_i32_e32
; GCN: ds_write_b32
define void @move_to_valu_vgpr_operand_phi(i32 addrspace(3)* %out) {
bb0:
br label %bb1
bb1: ; preds = %bb3, %bb0
%tmp0 = phi i32 [ 8, %bb0 ], [ %tmp4, %bb3 ]
%tmp1 = add nsw i32 %tmp0, -1
%tmp2 = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tmp1
br i1 undef, label %bb2, label %bb3
bb2: ; preds = %bb1
store volatile i32 1, i32 addrspace(3)* %tmp2, align 4
br label %bb3
bb3: ; preds = %bb2, %bb1
%tmp4 = add nsw i32 %tmp0, 2
br label %bb1
}
declare i32 @llvm.amdgcn.workitem.id.x() #0
attributes #0 = { nounwind readnone }