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[SLP] Fix crash after r358519, by V. Porpodas. 

Summary: The code did not check if operand was undef before casting it to Instruction.

Reviewers: RKSimon, ABataev, dtemirbulatov

Reviewed By: ABataev

Subscribers: uabelho

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D61024

llvm-svn: 359136
This commit is contained in:
Alexey Bataev 2019-04-24 20:21:32 +00:00
parent c06a470fc8
commit ef3c1884ec
2 changed files with 49 additions and 1 deletions
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3
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
View File

@ -785,9 +785,10 @@ public:
break; break;
case ReorderingMode::Opcode: case ReorderingMode::Opcode:
// We accept both Instructions and Undefs, but with different scores. // We accept both Instructions and Undefs, but with different scores.
if ((isa<Instruction>(Op) && if ((isa<Instruction>(Op) && isa<Instruction>(OpLastLane) &&
cast<Instruction>(Op)->getOpcode() == cast<Instruction>(Op)->getOpcode() ==
cast<Instruction>(OpLastLane)->getOpcode()) || cast<Instruction>(OpLastLane)->getOpcode()) ||
(isa<UndefValue>(OpLastLane) && isa<Instruction>(Op)) ||
isa<UndefValue>(Op)) { isa<UndefValue>(Op)) {
// An instruction has a higher score than an undef. // An instruction has a higher score than an undef.
unsigned Score = (isa<UndefValue>(Op)) ? GoodScore : BestScore; unsigned Score = (isa<UndefValue>(Op)) ? GoodScore : BestScore;

47
llvm/test/Transforms/SLPVectorizer/X86/crash_reordering_undefs.ll Normal file
View File

@ -0,0 +1,47 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux -mcpu=corei7-avx | FileCheck %s
define i32 @crash_reordering_undefs() {
; CHECK-LABEL: @crash_reordering_undefs(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[OR0:%.*]] = or i64 undef, undef
; CHECK-NEXT: [[CMP0:%.*]] = icmp eq i64 undef, [[OR0]]
; CHECK-NEXT: [[ADD0:%.*]] = select i1 [[CMP0]], i32 65536, i32 65537
; CHECK-NEXT: [[ADD1:%.*]] = add i32 undef, [[ADD0]]
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i64 undef, undef
; CHECK-NEXT: [[ADD2:%.*]] = select i1 [[CMP1]], i32 65536, i32 65537
; CHECK-NEXT: [[ADD3:%.*]] = add i32 [[ADD1]], [[ADD2]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i64 undef, undef
; CHECK-NEXT: [[ADD4:%.*]] = select i1 [[CMP2]], i32 65536, i32 65537
; CHECK-NEXT: [[ADD5:%.*]] = add i32 [[ADD3]], [[ADD4]]
; CHECK-NEXT: [[ADD6:%.*]] = add i32 [[ADD5]], undef
; CHECK-NEXT: [[ADD7:%.*]] = add i32 [[ADD6]], undef
; CHECK-NEXT: [[ADD8:%.*]] = add i32 [[ADD7]], undef
; CHECK-NEXT: [[OR1:%.*]] = or i64 undef, undef
; CHECK-NEXT: [[CMP3:%.*]] = icmp eq i64 undef, [[OR1]]
; CHECK-NEXT: [[ADD9:%.*]] = select i1 [[CMP3]], i32 65536, i32 65537
; CHECK-NEXT: [[ADD10:%.*]] = add i32 [[ADD8]], [[ADD9]]
; CHECK-NEXT: [[ADD11:%.*]] = add i32 [[ADD10]], undef
; CHECK-NEXT: ret i32 [[ADD11]]
;
entry:
%or0 = or i64 undef, undef
%cmp0 = icmp eq i64 undef, %or0
%add0 = select i1 %cmp0, i32 65536, i32 65537
%add1 = add i32 undef, %add0
%cmp1 = icmp eq i64 undef, undef
%add2 = select i1 %cmp1, i32 65536, i32 65537
%add3 = add i32 %add1, %add2
%cmp2 = icmp eq i64 undef, undef
%add4 = select i1 %cmp2, i32 65536, i32 65537
%add5 = add i32 %add3, %add4
%add6 = add i32 %add5, undef
%add7 = add i32 %add6, undef
%add8 = add i32 %add7, undef
%or1 = or i64 undef, undef
%cmp3 = icmp eq i64 undef, %or1
%add9 = select i1 %cmp3, i32 65536, i32 65537
%add10 = add i32 %add8, %add9
%add11 = add i32 %add10, undef
ret i32 %add11
}