Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
This commit is contained in:
parent
caaf8aae4d
commit
eee14601b1
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@ -490,26 +490,6 @@ public:
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return false;
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return false;
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}
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}
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const = 0;
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// getCrossCopyRegClass - Returns a legal register class to copy a register
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// in the specified class to or from. Returns NULL if it is possible to copy
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/// between a two registers of the specified class.
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/// between a two registers of the specified class.
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@ -27,6 +27,8 @@ class TargetMachine;
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class TargetRegisterClass;
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class TargetRegisterClass;
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class LiveVariables;
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class LiveVariables;
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template<class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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// Data types used to define information about a single machine instruction
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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@ -467,6 +469,34 @@ public:
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assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
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assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
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}
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}
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
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}
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
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}
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
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}
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
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}
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/// BlockHasNoFallThrough - Return true if the specified block does not
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/// BlockHasNoFallThrough - Return true if the specified block does not
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/// fall-through into its successor block. This is primarily used when a
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/// fall-through into its successor block. This is primarily used when a
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/// branch is unanalyzable. It is useful for things like unconditional
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/// branch is unanalyzable. It is useful for things like unconditional
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@ -243,7 +243,8 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
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return;
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return;
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const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
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const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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// Now that we have a stack slot for each register to be saved, insert spill
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// Now that we have a stack slot for each register to be saved, insert spill
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// code into the entry block.
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// code into the entry block.
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MachineBasicBlock *MBB = Fn.begin();
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MachineBasicBlock *MBB = Fn.begin();
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@ -254,13 +255,12 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
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MBB->addLiveIn(CSI[i].getReg());
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MBB->addLiveIn(CSI[i].getReg());
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// Insert the spill to the stack frame.
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// Insert the spill to the stack frame.
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RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
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TII.storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
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CSI[i].getFrameIdx(), CSI[i].getRegClass());
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CSI[i].getFrameIdx(), CSI[i].getRegClass());
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}
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}
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}
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}
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// Add code to restore the callee-save registers in each exiting block.
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// Add code to restore the callee-save registers in each exiting block.
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const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
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for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
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for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
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// If last instruction is a return instruction, add an epilogue.
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// If last instruction is a return instruction, add an epilogue.
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if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
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if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
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@ -282,7 +282,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
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// that preceed it.
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// that preceed it.
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if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
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if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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RegInfo->loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
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TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
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CSI[i].getFrameIdx(),
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CSI[i].getFrameIdx(),
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CSI[i].getRegClass());
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CSI[i].getRegClass());
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assert(I != MBB->begin() &&
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assert(I != MBB->begin() &&
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@ -319,6 +319,9 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
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" the intended one.");
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" the intended one.");
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DOUT << " Spilling register " << RegInfo->getName(PhysReg)
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DOUT << " Spilling register " << RegInfo->getName(PhysReg)
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<< " containing %reg" << VirtReg;
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<< " containing %reg" << VirtReg;
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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if (!isVirtRegModified(VirtReg))
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if (!isVirtRegModified(VirtReg))
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DOUT << " which has not been modified, so no store necessary!";
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DOUT << " which has not been modified, so no store necessary!";
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@ -329,7 +332,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DOUT << " to stack slot #" << FrameIndex;
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DOUT << " to stack slot #" << FrameIndex;
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RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
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TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
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++NumStores; // Update statistics
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++NumStores; // Update statistics
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}
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}
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@ -542,7 +545,8 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
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<< RegInfo->getName(PhysReg) << "\n";
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<< RegInfo->getName(PhysReg) << "\n";
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// Add move instruction(s)
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// Add move instruction(s)
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RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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++NumLoads; // Update statistics
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++NumLoads; // Update statistics
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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@ -276,6 +276,9 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
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" the intended one.");
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" the intended one.");
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DOUT << " Spilling register " << MRI->getName(PhysReg)
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DOUT << " Spilling register " << MRI->getName(PhysReg)
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<< " containing %reg" << VirtReg;
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<< " containing %reg" << VirtReg;
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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if (!isVirtRegModified(VirtReg))
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if (!isVirtRegModified(VirtReg))
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DOUT << " which has not been modified, so no store necessary!";
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DOUT << " which has not been modified, so no store necessary!";
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@ -286,7 +289,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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int FrameIndex = getStackSpaceFor(VirtReg, RC);
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DOUT << " to stack slot #" << FrameIndex;
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DOUT << " to stack slot #" << FrameIndex;
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MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
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TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
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++NumStores; // Update statistics
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++NumStores; // Update statistics
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}
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}
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@ -495,7 +498,8 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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<< MRI->getName(PhysReg) << "\n";
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<< MRI->getName(PhysReg) << "\n";
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// Add move instruction(s)
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// Add move instruction(s)
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MRI->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
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++NumLoads; // Update statistics
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++NumLoads; // Update statistics
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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MF->getRegInfo().setPhysRegUsed(PhysReg);
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@ -144,7 +144,8 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
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// Add move instruction(s)
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// Add move instruction(s)
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++NumLoads;
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++NumLoads;
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MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
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return PhysReg;
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return PhysReg;
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}
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}
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@ -152,11 +153,13 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock::iterator I,
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unsigned VirtReg, unsigned PhysReg) {
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unsigned VirtReg, unsigned PhysReg) {
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
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const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
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const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
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int FrameIdx = getStackSpaceFor(VirtReg, RC);
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int FrameIdx = getStackSpaceFor(VirtReg, RC);
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// Add move instruction(s)
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// Add move instruction(s)
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++NumStores;
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++NumStores;
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MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
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TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
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}
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}
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@ -72,7 +72,7 @@ void RegScavenger::restoreScavengedReg() {
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if (!ScavengedReg)
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if (!ScavengedReg)
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return;
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return;
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RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
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TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
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ScavengingFrameIndex, ScavengedRC);
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ScavengingFrameIndex, ScavengedRC);
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MachineBasicBlock::iterator II = prior(MBBI);
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MachineBasicBlock::iterator II = prior(MBBI);
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RegInfo->eliminateFrameIndex(II, 0, this);
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RegInfo->eliminateFrameIndex(II, 0, this);
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@ -276,13 +276,13 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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if (ScavengedReg != 0) {
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if (ScavengedReg != 0) {
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// First restore previously scavenged register.
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// First restore previously scavenged register.
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RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
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TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
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ScavengingFrameIndex, ScavengedRC);
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ScavengingFrameIndex, ScavengedRC);
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MachineBasicBlock::iterator II = prior(I);
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MachineBasicBlock::iterator II = prior(I);
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RegInfo->eliminateFrameIndex(II, SPAdj, this);
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RegInfo->eliminateFrameIndex(II, SPAdj, this);
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}
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}
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RegInfo->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
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MachineBasicBlock::iterator II = prior(I);
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MachineBasicBlock::iterator II = prior(I);
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RegInfo->eliminateFrameIndex(II, SPAdj, this);
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RegInfo->eliminateFrameIndex(II, SPAdj, this);
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ScavengedReg = SReg;
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ScavengedReg = SReg;
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@ -173,7 +173,8 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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DOUT << "********** REWRITE MACHINE CODE **********\n";
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DOUT << "********** REWRITE MACHINE CODE **********\n";
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
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const TargetMachine &TM = MF.getTarget();
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const TargetMachine &TM = MF.getTarget();
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const MRegisterInfo &MRI = *TM.getRegisterInfo();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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// LoadedRegs - Keep track of which vregs are loaded, so that we only load
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// LoadedRegs - Keep track of which vregs are loaded, so that we only load
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// each vreg once (in the case where a spilled vreg is used by multiple
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// each vreg once (in the case where a spilled vreg is used by multiple
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@ -202,14 +203,14 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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if (MO.isUse() &&
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if (MO.isUse() &&
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std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
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std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
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== LoadedRegs.end()) {
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== LoadedRegs.end()) {
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MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
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TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
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LoadedRegs.push_back(VirtReg);
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LoadedRegs.push_back(VirtReg);
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++NumLoads;
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++NumLoads;
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DOUT << '\t' << *prior(MII);
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DOUT << '\t' << *prior(MII);
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}
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}
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if (MO.isDef()) {
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if (MO.isDef()) {
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MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
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TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
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StackSlot, RC);
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StackSlot, RC);
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++NumStores;
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++NumStores;
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}
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}
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@ -645,6 +646,9 @@ namespace {
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BitVector &RegKills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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VirtRegMap &VRM) {
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const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
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.getInstrInfo();
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if (Reuses.empty()) return PhysReg; // This is most often empty.
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if (Reuses.empty()) return PhysReg; // This is most often empty.
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for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
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for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
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@ -693,7 +697,7 @@ namespace {
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VRM.getReMaterializedMI(NewOp.VirtReg));
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VRM.getReMaterializedMI(NewOp.VirtReg));
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++NumReMats;
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++NumReMats;
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} else {
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} else {
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MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
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TII->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
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NewOp.StackSlotOrReMat, AliasRC);
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NewOp.StackSlotOrReMat, AliasRC);
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// Any stores to this stack slot are not dead anymore.
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// Any stores to this stack slot are not dead anymore.
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MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
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MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
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@ -876,7 +880,7 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
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BitVector &RegKills,
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BitVector &RegKills,
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std::vector<MachineOperand*> &KillOps,
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std::vector<MachineOperand*> &KillOps,
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VirtRegMap &VRM) {
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VirtRegMap &VRM) {
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MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
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TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
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DOUT << "Store:\t" << *next(MII);
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DOUT << "Store:\t" << *next(MII);
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// If there is a dead store to this stack slot, nuke it now.
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// If there is a dead store to this stack slot, nuke it now.
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@ -979,7 +983,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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++NumReMats;
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++NumReMats;
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} else {
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} else {
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
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const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||||
MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
|
TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
|
||||||
RC);
|
RC);
|
||||||
++NumLoads;
|
++NumLoads;
|
||||||
}
|
}
|
||||||
|
@ -1002,7 +1006,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||||
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
|
||||||
unsigned Phys = VRM.getPhys(VirtReg);
|
unsigned Phys = VRM.getPhys(VirtReg);
|
||||||
int StackSlot = VRM.getStackSlot(VirtReg);
|
int StackSlot = VRM.getStackSlot(VirtReg);
|
||||||
MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
|
TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
|
||||||
MachineInstr *StoreMI = next(MII);
|
MachineInstr *StoreMI = next(MII);
|
||||||
DOUT << "Store:\t" << StoreMI;
|
DOUT << "Store:\t" << StoreMI;
|
||||||
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
|
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
|
||||||
|
@ -1218,7 +1222,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
|
||||||
++NumReMats;
|
++NumReMats;
|
||||||
} else {
|
} else {
|
||||||
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
|
||||||
MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
|
TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
|
||||||
++NumLoads;
|
++NumLoads;
|
||||||
}
|
}
|
||||||
// This invalidates PhysReg.
|
// This invalidates PhysReg.
|
||||||
|
|
|
@ -470,6 +470,134 @@ void ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
|
||||||
|
MachineOperand &MO) {
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB = MIB.addImm(MO.getImm());
|
||||||
|
else if (MO.isFrameIndex())
|
||||||
|
MIB = MIB.addFrameIndex(MO.getIndex());
|
||||||
|
else
|
||||||
|
assert(0 && "Unknown operand for ARMInstrAddOperand!");
|
||||||
|
|
||||||
|
return MIB;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMInstrInfo::
|
||||||
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
if (AFI->isThumbFunction())
|
||||||
|
BuildMI(MBB, I, get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
else
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::STR))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTD))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FSTS))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
if (AFI->isThumbFunction()) {
|
||||||
|
Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
Opc = ARM::STR;
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
Opc = ARM::FSTD;
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
Opc = ARM::FSTS;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
||||||
|
AddDefaultPred(MIB);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMInstrInfo::
|
||||||
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
MachineFunction &MF = *MBB.getParent();
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
if (AFI->isThumbFunction())
|
||||||
|
BuildMI(MBB, I, get(ARM::tRestore), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0);
|
||||||
|
else
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::LDR), DestReg)
|
||||||
|
.addFrameIndex(FI).addReg(0).addImm(0));
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDD), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
AddDefaultPred(BuildMI(MBB, I, get(ARM::FLDS), DestReg)
|
||||||
|
.addFrameIndex(FI).addImm(0));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == ARM::GPRRegisterClass) {
|
||||||
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
||||||
|
if (AFI->isThumbFunction()) {
|
||||||
|
Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
Opc = ARM::LDR;
|
||||||
|
} else if (RC == ARM::DPRRegisterClass) {
|
||||||
|
Opc = ARM::FLDD;
|
||||||
|
} else {
|
||||||
|
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
||||||
|
Opc = ARM::FLDS;
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
||||||
|
AddDefaultPred(MIB);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
||||||
if (MBB.empty()) return false;
|
if (MBB.empty()) return false;
|
||||||
|
|
||||||
|
|
|
@ -165,6 +165,25 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
||||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||||
|
|
||||||
|
|
|
@ -142,134 +142,6 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
|
||||||
return MIB.addReg(0);
|
return MIB.addReg(0);
|
||||||
}
|
}
|
||||||
|
|
||||||
static const MachineInstrBuilder &ARMInstrAddOperand(MachineInstrBuilder &MIB,
|
|
||||||
MachineOperand &MO) {
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB = MIB.addImm(MO.getImm());
|
|
||||||
else if (MO.isFrameIndex())
|
|
||||||
MIB = MIB.addFrameIndex(MO.getIndex());
|
|
||||||
else
|
|
||||||
assert(0 && "Unknown operand for ARMInstrAddOperand!");
|
|
||||||
|
|
||||||
return MIB;
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::
|
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned SrcReg, bool isKill, int FI,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
if (RC == ARM::GPRRegisterClass) {
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
if (AFI->isThumbFunction())
|
|
||||||
BuildMI(MBB, I, TII.get(ARM::tSpill)).addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FI).addImm(0);
|
|
||||||
else
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::STR))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
||||||
} else if (RC == ARM::DPRRegisterClass) {
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTD))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FI).addImm(0));
|
|
||||||
} else {
|
|
||||||
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FSTS))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FI).addImm(0));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == ARM::GPRRegisterClass) {
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
if (AFI->isThumbFunction()) {
|
|
||||||
Opc = Addr[0].isFrameIndex() ? ARM::tSpill : ARM::tSTR;
|
|
||||||
MachineInstrBuilder MIB =
|
|
||||||
BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
Opc = ARM::STR;
|
|
||||||
} else if (RC == ARM::DPRRegisterClass) {
|
|
||||||
Opc = ARM::FSTD;
|
|
||||||
} else {
|
|
||||||
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
||||||
Opc = ARM::FSTS;
|
|
||||||
}
|
|
||||||
|
|
||||||
MachineInstrBuilder MIB =
|
|
||||||
BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
||||||
AddDefaultPred(MIB);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::
|
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned DestReg, int FI,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
if (RC == ARM::GPRRegisterClass) {
|
|
||||||
MachineFunction &MF = *MBB.getParent();
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
if (AFI->isThumbFunction())
|
|
||||||
BuildMI(MBB, I, TII.get(ARM::tRestore), DestReg)
|
|
||||||
.addFrameIndex(FI).addImm(0);
|
|
||||||
else
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::LDR), DestReg)
|
|
||||||
.addFrameIndex(FI).addReg(0).addImm(0));
|
|
||||||
} else if (RC == ARM::DPRRegisterClass) {
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDD), DestReg)
|
|
||||||
.addFrameIndex(FI).addImm(0));
|
|
||||||
} else {
|
|
||||||
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
||||||
AddDefaultPred(BuildMI(MBB, I, TII.get(ARM::FLDS), DestReg)
|
|
||||||
.addFrameIndex(FI).addImm(0));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == ARM::GPRRegisterClass) {
|
|
||||||
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
||||||
if (AFI->isThumbFunction()) {
|
|
||||||
Opc = Addr[0].isFrameIndex() ? ARM::tRestore : ARM::tLDR;
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
Opc = ARM::LDR;
|
|
||||||
} else if (RC == ARM::DPRRegisterClass) {
|
|
||||||
Opc = ARM::FLDD;
|
|
||||||
} else {
|
|
||||||
assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
|
|
||||||
Opc = ARM::FLDS;
|
|
||||||
}
|
|
||||||
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = ARMInstrAddOperand(MIB, Addr[i]);
|
|
||||||
AddDefaultPred(MIB);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
||||||
/// specified immediate.
|
/// specified immediate.
|
||||||
static void emitLoadConstPool(MachineBasicBlock &MBB,
|
static void emitLoadConstPool(MachineBasicBlock &MBB,
|
||||||
|
|
|
@ -45,31 +45,6 @@ public:
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const;
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
|
|
@ -155,6 +155,101 @@ void AlphaInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
//cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
|
||||||
|
// << FrameIdx << "\n";
|
||||||
|
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
|
||||||
|
if (RC == Alpha::F4RCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::STS))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else if (RC == Alpha::F8RCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::STT))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else if (RC == Alpha::GPRCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::STQ))
|
||||||
|
.addReg(SrcReg, false, false, isKill)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == Alpha::F4RCRegisterClass)
|
||||||
|
Opc = Alpha::STS;
|
||||||
|
else if (RC == Alpha::F8RCRegisterClass)
|
||||||
|
Opc = Alpha::STT;
|
||||||
|
else if (RC == Alpha::GPRCRegisterClass)
|
||||||
|
Opc = Alpha::STQ;
|
||||||
|
else
|
||||||
|
abort();
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(get(Opc)).addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
||||||
|
else
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
|
||||||
|
// << FrameIdx << "\n";
|
||||||
|
if (RC == Alpha::F4RCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::LDS), DestReg)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else if (RC == Alpha::F8RCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::LDT), DestReg)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else if (RC == Alpha::GPRCRegisterClass)
|
||||||
|
BuildMI(MBB, MI, get(Alpha::LDQ), DestReg)
|
||||||
|
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
||||||
|
else
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == Alpha::F4RCRegisterClass)
|
||||||
|
Opc = Alpha::LDS;
|
||||||
|
else if (RC == Alpha::F8RCRegisterClass)
|
||||||
|
Opc = Alpha::LDT;
|
||||||
|
else if (RC == Alpha::GPRCRegisterClass)
|
||||||
|
Opc = Alpha::LDQ;
|
||||||
|
else
|
||||||
|
abort();
|
||||||
|
MachineInstrBuilder MIB =
|
||||||
|
BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
||||||
|
else
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
|
||||||
static unsigned AlphaRevCondCode(unsigned Opcode) {
|
static unsigned AlphaRevCondCode(unsigned Opcode) {
|
||||||
switch (Opcode) {
|
switch (Opcode) {
|
||||||
case Alpha::BEQ: return Alpha::BNE;
|
case Alpha::BEQ: return Alpha::BNE;
|
||||||
|
|
|
@ -47,6 +47,25 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
|
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
|
||||||
MachineBasicBlock *&FBB,
|
MachineBasicBlock *&FBB,
|
||||||
std::vector<MachineOperand> &Cond) const;
|
std::vector<MachineOperand> &Cond) const;
|
||||||
|
|
|
@ -58,101 +58,6 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
|
||||||
AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
//cerr << "Trying to store " << getPrettyName(SrcReg) << " to "
|
|
||||||
// << FrameIdx << "\n";
|
|
||||||
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
|
|
||||||
if (RC == Alpha::F4RCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::STS))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else if (RC == Alpha::F8RCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::STT))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else if (RC == Alpha::GPRCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::STQ))
|
|
||||||
.addReg(SrcReg, false, false, isKill)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == Alpha::F4RCRegisterClass)
|
|
||||||
Opc = Alpha::STS;
|
|
||||||
else if (RC == Alpha::F8RCRegisterClass)
|
|
||||||
Opc = Alpha::STT;
|
|
||||||
else if (RC == Alpha::GPRCRegisterClass)
|
|
||||||
Opc = Alpha::STQ;
|
|
||||||
else
|
|
||||||
abort();
|
|
||||||
MachineInstrBuilder MIB =
|
|
||||||
BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
|
||||||
else
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
//cerr << "Trying to load " << getPrettyName(DestReg) << " to "
|
|
||||||
// << FrameIdx << "\n";
|
|
||||||
if (RC == Alpha::F4RCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::LDS), DestReg)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else if (RC == Alpha::F8RCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::LDT), DestReg)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else if (RC == Alpha::GPRCRegisterClass)
|
|
||||||
BuildMI(MBB, MI, TII.get(Alpha::LDQ), DestReg)
|
|
||||||
.addFrameIndex(FrameIdx).addReg(Alpha::F31);
|
|
||||||
else
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == Alpha::F4RCRegisterClass)
|
|
||||||
Opc = Alpha::LDS;
|
|
||||||
else if (RC == Alpha::F8RCRegisterClass)
|
|
||||||
Opc = Alpha::LDT;
|
|
||||||
else if (RC == Alpha::GPRCRegisterClass)
|
|
||||||
Opc = Alpha::LDQ;
|
|
||||||
else
|
|
||||||
abort();
|
|
||||||
MachineInstrBuilder MIB =
|
|
||||||
BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
|
|
||||||
else
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
|
|
||||||
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
SmallVectorImpl<unsigned> &Ops,
|
||||||
int FrameIndex) const {
|
int FrameIndex) const {
|
||||||
|
|
|
@ -28,26 +28,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||||
AlphaRegisterInfo(const TargetInstrInfo &tii);
|
AlphaRegisterInfo(const TargetInstrInfo &tii);
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
MachineInstr* foldMemoryOperand(MachineInstr* MI,
|
MachineInstr* foldMemoryOperand(MachineInstr* MI,
|
||||||
SmallVectorImpl<unsigned> &Ops,
|
SmallVectorImpl<unsigned> &Ops,
|
||||||
int FrameIndex) const;
|
int FrameIndex) const;
|
||||||
|
@ -58,11 +38,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
|
|
@ -13,6 +13,7 @@
|
||||||
|
|
||||||
#include "SPURegisterNames.h"
|
#include "SPURegisterNames.h"
|
||||||
#include "SPUInstrInfo.h"
|
#include "SPUInstrInfo.h"
|
||||||
|
#include "SPUInstrBuilder.h"
|
||||||
#include "SPUTargetMachine.h"
|
#include "SPUTargetMachine.h"
|
||||||
#include "SPUGenInstrInfo.inc"
|
#include "SPUGenInstrInfo.inc"
|
||||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||||
|
@ -188,7 +189,7 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
const TargetRegisterClass *SrcRC) const
|
const TargetRegisterClass *SrcRC) const
|
||||||
{
|
{
|
||||||
if (DestRC != SrcRC) {
|
if (DestRC != SrcRC) {
|
||||||
cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
|
cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -217,3 +218,173 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
abort();
|
abort();
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const
|
||||||
|
{
|
||||||
|
MachineOpCode opc;
|
||||||
|
if (RC == SPU::GPRCRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::STQDr128
|
||||||
|
: SPU::STQXr128;
|
||||||
|
} else if (RC == SPU::R64CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::STQDr64
|
||||||
|
: SPU::STQXr64;
|
||||||
|
} else if (RC == SPU::R64FPRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::STQDr64
|
||||||
|
: SPU::STQXr64;
|
||||||
|
} else if (RC == SPU::R32CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::STQDr32
|
||||||
|
: SPU::STQXr32;
|
||||||
|
} else if (RC == SPU::R32FPRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::STQDr32
|
||||||
|
: SPU::STQXr32;
|
||||||
|
} else if (RC == SPU::R16CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
|
||||||
|
SPU::STQDr16
|
||||||
|
: SPU::STQXr16;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
addFrameReference(BuildMI(MBB, MI, get(opc))
|
||||||
|
.addReg(SrcReg, false, false, isKill), FrameIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
cerr << "storeRegToAddr() invoked!\n";
|
||||||
|
abort();
|
||||||
|
|
||||||
|
if (Addr[0].isFrameIndex()) {
|
||||||
|
/* do what storeRegToStackSlot does here */
|
||||||
|
} else {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == SPU::GPRCRegisterClass) {
|
||||||
|
/* Opc = PPC::STW; */
|
||||||
|
} else if (RC == SPU::R16CRegisterClass) {
|
||||||
|
/* Opc = PPC::STD; */
|
||||||
|
} else if (RC == SPU::R32CRegisterClass) {
|
||||||
|
/* Opc = PPC::STFD; */
|
||||||
|
} else if (RC == SPU::R32FPRegisterClass) {
|
||||||
|
/* Opc = PPC::STFD; */
|
||||||
|
} else if (RC == SPU::R64FPRegisterClass) {
|
||||||
|
/* Opc = PPC::STFS; */
|
||||||
|
} else if (RC == SPU::VECREGRegisterClass) {
|
||||||
|
/* Opc = PPC::STVX; */
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc))
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const
|
||||||
|
{
|
||||||
|
MachineOpCode opc;
|
||||||
|
if (RC == SPU::GPRCRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr128
|
||||||
|
: SPU::LQXr128;
|
||||||
|
} else if (RC == SPU::R64CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr64
|
||||||
|
: SPU::LQXr64;
|
||||||
|
} else if (RC == SPU::R64FPRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr64
|
||||||
|
: SPU::LQXr64;
|
||||||
|
} else if (RC == SPU::R32CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr32
|
||||||
|
: SPU::LQXr32;
|
||||||
|
} else if (RC == SPU::R32FPRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr32
|
||||||
|
: SPU::LQXr32;
|
||||||
|
} else if (RC == SPU::R16CRegisterClass) {
|
||||||
|
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
||||||
|
? SPU::LQDr16
|
||||||
|
: SPU::LQXr16;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass in loadRegFromStackSlot!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*!
|
||||||
|
\note We are really pessimistic here about what kind of a load we're doing.
|
||||||
|
*/
|
||||||
|
void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs)
|
||||||
|
const {
|
||||||
|
cerr << "loadRegToAddr() invoked!\n";
|
||||||
|
abort();
|
||||||
|
|
||||||
|
if (Addr[0].isFrameIndex()) {
|
||||||
|
/* do what loadRegFromStackSlot does here... */
|
||||||
|
} else {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == SPU::R8CRegisterClass) {
|
||||||
|
/* do brilliance here */
|
||||||
|
} else if (RC == SPU::R16CRegisterClass) {
|
||||||
|
/* Opc = PPC::LWZ; */
|
||||||
|
} else if (RC == SPU::R32CRegisterClass) {
|
||||||
|
/* Opc = PPC::LD; */
|
||||||
|
} else if (RC == SPU::R32FPRegisterClass) {
|
||||||
|
/* Opc = PPC::LFD; */
|
||||||
|
} else if (RC == SPU::R64FPRegisterClass) {
|
||||||
|
/* Opc = PPC::LFS; */
|
||||||
|
} else if (RC == SPU::VECREGRegisterClass) {
|
||||||
|
/* Opc = PPC::LVX; */
|
||||||
|
} else if (RC == SPU::GPRCRegisterClass) {
|
||||||
|
/* Opc = something else! */
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
@ -51,6 +51,30 @@ namespace llvm {
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
|
||||||
|
//! Store a register to a stack slot, based on its register class.
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
//! Store a register to an address, based on its register class
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
//! Load a register from a stack slot, based on its register class.
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
//! Loqad a register from an address, based on its register class
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -191,175 +191,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
void
|
|
||||||
SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const
|
|
||||||
{
|
|
||||||
MachineOpCode opc;
|
|
||||||
if (RC == SPU::GPRCRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::STQDr128
|
|
||||||
: SPU::STQXr128;
|
|
||||||
} else if (RC == SPU::R64CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::STQDr64
|
|
||||||
: SPU::STQXr64;
|
|
||||||
} else if (RC == SPU::R64FPRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::STQDr64
|
|
||||||
: SPU::STQXr64;
|
|
||||||
} else if (RC == SPU::R32CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::STQDr32
|
|
||||||
: SPU::STQXr32;
|
|
||||||
} else if (RC == SPU::R32FPRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::STQDr32
|
|
||||||
: SPU::STQXr32;
|
|
||||||
} else if (RC == SPU::R16CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
|
|
||||||
SPU::STQDr16
|
|
||||||
: SPU::STQXr16;
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
addFrameReference(BuildMI(MBB, MI, TII.get(opc))
|
|
||||||
.addReg(SrcReg, false, false, isKill), FrameIdx);
|
|
||||||
}
|
|
||||||
|
|
||||||
void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
cerr << "storeRegToAddr() invoked!\n";
|
|
||||||
abort();
|
|
||||||
|
|
||||||
if (Addr[0].isFrameIndex()) {
|
|
||||||
/* do what storeRegToStackSlot does here */
|
|
||||||
} else {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == SPU::GPRCRegisterClass) {
|
|
||||||
/* Opc = PPC::STW; */
|
|
||||||
} else if (RC == SPU::R16CRegisterClass) {
|
|
||||||
/* Opc = PPC::STD; */
|
|
||||||
} else if (RC == SPU::R32CRegisterClass) {
|
|
||||||
/* Opc = PPC::STFD; */
|
|
||||||
} else if (RC == SPU::R32FPRegisterClass) {
|
|
||||||
/* Opc = PPC::STFD; */
|
|
||||||
} else if (RC == SPU::R64FPRegisterClass) {
|
|
||||||
/* Opc = PPC::STFS; */
|
|
||||||
} else if (RC == SPU::VECREGRegisterClass) {
|
|
||||||
/* Opc = PPC::STVX; */
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const
|
|
||||||
{
|
|
||||||
MachineOpCode opc;
|
|
||||||
if (RC == SPU::GPRCRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr128
|
|
||||||
: SPU::LQXr128;
|
|
||||||
} else if (RC == SPU::R64CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr64
|
|
||||||
: SPU::LQXr64;
|
|
||||||
} else if (RC == SPU::R64FPRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr64
|
|
||||||
: SPU::LQXr64;
|
|
||||||
} else if (RC == SPU::R32CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr32
|
|
||||||
: SPU::LQXr32;
|
|
||||||
} else if (RC == SPU::R32FPRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr32
|
|
||||||
: SPU::LQXr32;
|
|
||||||
} else if (RC == SPU::R16CRegisterClass) {
|
|
||||||
opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
|
|
||||||
? SPU::LQDr16
|
|
||||||
: SPU::LQXr16;
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass in loadRegFromStackSlot!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*!
|
|
||||||
\note We are really pessimistic here about what kind of a load we're doing.
|
|
||||||
*/
|
|
||||||
void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs)
|
|
||||||
const {
|
|
||||||
cerr << "loadRegToAddr() invoked!\n";
|
|
||||||
abort();
|
|
||||||
|
|
||||||
if (Addr[0].isFrameIndex()) {
|
|
||||||
/* do what loadRegFromStackSlot does here... */
|
|
||||||
} else {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == SPU::R8CRegisterClass) {
|
|
||||||
/* do brilliance here */
|
|
||||||
} else if (RC == SPU::R16CRegisterClass) {
|
|
||||||
/* Opc = PPC::LWZ; */
|
|
||||||
} else if (RC == SPU::R32CRegisterClass) {
|
|
||||||
/* Opc = PPC::LD; */
|
|
||||||
} else if (RC == SPU::R32FPRegisterClass) {
|
|
||||||
/* Opc = PPC::LFD; */
|
|
||||||
} else if (RC == SPU::R64FPRegisterClass) {
|
|
||||||
/* Opc = PPC::LFS; */
|
|
||||||
} else if (RC == SPU::VECREGRegisterClass) {
|
|
||||||
/* Opc = PPC::LVX; */
|
|
||||||
} else if (RC == SPU::GPRCRegisterClass) {
|
|
||||||
/* Opc = something else! */
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg,
|
unsigned DestReg,
|
||||||
|
|
|
@ -40,37 +40,6 @@ namespace llvm {
|
||||||
*/
|
*/
|
||||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||||
|
|
||||||
//! Store a register to a stack slot, based on its register class.
|
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
//! Store a register to an address, based on its register class
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
//! Load a register from a stack slot, based on its register class.
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
//! Loqad a register from an address, based on its register class
|
|
||||||
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
//! Copy a register to another
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
|
|
@ -74,3 +74,111 @@ void IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
else // otherwise, MOV works (for both gen. regs and FP regs)
|
else // otherwise, MOV works (for both gen. regs and FP regs)
|
||||||
BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
|
BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill,
|
||||||
|
int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const{
|
||||||
|
|
||||||
|
if (RC == IA64::FPRegisterClass) {
|
||||||
|
BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
} else if (RC == IA64::GRRegisterClass) {
|
||||||
|
BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
} else if (RC == IA64::PRRegisterClass) {
|
||||||
|
/* we use IA64::r2 as a temporary register for doing this hackery. */
|
||||||
|
// first we load 0:
|
||||||
|
BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0);
|
||||||
|
// then conditionally add 1:
|
||||||
|
BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
|
||||||
|
.addImm(1).addReg(SrcReg, false, false, isKill);
|
||||||
|
// and then store it to the stack
|
||||||
|
BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
|
||||||
|
} else assert(0 &&
|
||||||
|
"sorry, I don't know how to store this sort of reg in the stack\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == IA64::FPRegisterClass) {
|
||||||
|
Opc = IA64::STF8;
|
||||||
|
} else if (RC == IA64::GRRegisterClass) {
|
||||||
|
Opc = IA64::ST8;
|
||||||
|
} else if (RC == IA64::PRRegisterClass) {
|
||||||
|
Opc = IA64::ST1;
|
||||||
|
} else {
|
||||||
|
assert(0 &&
|
||||||
|
"sorry, I don't know how to store this sort of reg\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc));
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
MIB.addReg(SrcReg, false, false, isKill);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC)const{
|
||||||
|
|
||||||
|
if (RC == IA64::FPRegisterClass) {
|
||||||
|
BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
|
||||||
|
} else if (RC == IA64::GRRegisterClass) {
|
||||||
|
BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
|
||||||
|
} else if (RC == IA64::PRRegisterClass) {
|
||||||
|
// first we load a byte from the stack into r2, our 'predicate hackery'
|
||||||
|
// scratch reg
|
||||||
|
BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
|
||||||
|
// then we compare it to zero. If it _is_ zero, compare-not-equal to
|
||||||
|
// r0 gives us 0, which is what we want, so that's nice.
|
||||||
|
BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
|
||||||
|
} else assert(0 &&
|
||||||
|
"sorry, I don't know how to load this sort of reg from the stack\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == IA64::FPRegisterClass) {
|
||||||
|
Opc = IA64::LDF8;
|
||||||
|
} else if (RC == IA64::GRRegisterClass) {
|
||||||
|
Opc = IA64::LD8;
|
||||||
|
} else if (RC == IA64::PRRegisterClass) {
|
||||||
|
Opc = IA64::LD1;
|
||||||
|
} else {
|
||||||
|
assert(0 &&
|
||||||
|
"sorry, I don't know how to store this sort of reg\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
|
@ -45,6 +45,25 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
} // End llvm namespace
|
} // End llvm namespace
|
||||||
|
|
|
@ -36,114 +36,6 @@ IA64RegisterInfo::IA64RegisterInfo(const TargetInstrInfo &tii)
|
||||||
: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
|
: IA64GenRegisterInfo(IA64::ADJUSTCALLSTACKDOWN, IA64::ADJUSTCALLSTACKUP),
|
||||||
TII(tii) {}
|
TII(tii) {}
|
||||||
|
|
||||||
void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill,
|
|
||||||
int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const{
|
|
||||||
|
|
||||||
if (RC == IA64::FPRegisterClass) {
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::STF_SPILL)).addFrameIndex(FrameIdx)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
} else if (RC == IA64::GRRegisterClass) {
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
} else if (RC == IA64::PRRegisterClass) {
|
|
||||||
/* we use IA64::r2 as a temporary register for doing this hackery. */
|
|
||||||
// first we load 0:
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::MOV), IA64::r2).addReg(IA64::r0);
|
|
||||||
// then conditionally add 1:
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2)
|
|
||||||
.addImm(1).addReg(SrcReg, false, false, isKill);
|
|
||||||
// and then store it to the stack
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2);
|
|
||||||
} else assert(0 &&
|
|
||||||
"sorry, I don't know how to store this sort of reg in the stack\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == IA64::FPRegisterClass) {
|
|
||||||
Opc = IA64::STF8;
|
|
||||||
} else if (RC == IA64::GRRegisterClass) {
|
|
||||||
Opc = IA64::ST8;
|
|
||||||
} else if (RC == IA64::PRRegisterClass) {
|
|
||||||
Opc = IA64::ST1;
|
|
||||||
} else {
|
|
||||||
assert(0 &&
|
|
||||||
"sorry, I don't know how to store this sort of reg\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
MIB.addReg(SrcReg, false, false, isKill);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC)const{
|
|
||||||
|
|
||||||
if (RC == IA64::FPRegisterClass) {
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx);
|
|
||||||
} else if (RC == IA64::GRRegisterClass) {
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::LD8), DestReg).addFrameIndex(FrameIdx);
|
|
||||||
} else if (RC == IA64::PRRegisterClass) {
|
|
||||||
// first we load a byte from the stack into r2, our 'predicate hackery'
|
|
||||||
// scratch reg
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx);
|
|
||||||
// then we compare it to zero. If it _is_ zero, compare-not-equal to
|
|
||||||
// r0 gives us 0, which is what we want, so that's nice.
|
|
||||||
BuildMI(MBB, MI, TII.get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0);
|
|
||||||
} else assert(0 &&
|
|
||||||
"sorry, I don't know how to load this sort of reg from the stack\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == IA64::FPRegisterClass) {
|
|
||||||
Opc = IA64::LDF8;
|
|
||||||
} else if (RC == IA64::GRRegisterClass) {
|
|
||||||
Opc = IA64::LD8;
|
|
||||||
} else if (RC == IA64::PRRegisterClass) {
|
|
||||||
Opc = IA64::LD1;
|
|
||||||
} else {
|
|
||||||
assert(0 &&
|
|
||||||
"sorry, I don't know how to store this sort of reg\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
void IA64RegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg,
|
unsigned DestReg,
|
||||||
|
|
|
@ -29,26 +29,6 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
|
||||||
IA64RegisterInfo(const TargetInstrInfo &tii);
|
IA64RegisterInfo(const TargetInstrInfo &tii);
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB,
|
void copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
|
|
|
@ -306,6 +306,71 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
assert (0 && "Can't copy this register");
|
assert (0 && "Can't copy this register");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void MipsInstrInfo::
|
||||||
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
|
const TargetRegisterClass *RC) const
|
||||||
|
{
|
||||||
|
if (RC == Mips::CPURegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(Mips::SW)).addReg(SrcReg, false, false, isKill)
|
||||||
|
.addImm(0).addFrameIndex(FI);
|
||||||
|
else
|
||||||
|
assert(0 && "Can't store this register to stack slot");
|
||||||
|
}
|
||||||
|
|
||||||
|
void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
if (RC != Mips::CPURegsRegisterClass)
|
||||||
|
assert(0 && "Can't store this register");
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Mips::SW))
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void MipsInstrInfo::
|
||||||
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, int FI,
|
||||||
|
const TargetRegisterClass *RC) const
|
||||||
|
{
|
||||||
|
if (RC == Mips::CPURegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
|
||||||
|
else
|
||||||
|
assert(0 && "Can't load this register from stack slot");
|
||||||
|
}
|
||||||
|
|
||||||
|
void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
if (RC != Mips::CPURegsRegisterClass)
|
||||||
|
assert(0 && "Can't load this register");
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Mips::LW), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
unsigned MipsInstrInfo::
|
unsigned MipsInstrInfo::
|
||||||
RemoveBranch(MachineBasicBlock &MBB) const
|
RemoveBranch(MachineBasicBlock &MBB) const
|
||||||
{
|
{
|
||||||
|
|
|
@ -86,6 +86,25 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
||||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||||
|
|
||||||
|
|
|
@ -83,71 +83,6 @@ getRegisterNumbering(unsigned RegEnum)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
void MipsRegisterInfo::
|
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned SrcReg, bool isKill, int FI,
|
|
||||||
const TargetRegisterClass *RC) const
|
|
||||||
{
|
|
||||||
if (RC == Mips::CPURegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(Mips::SW)).addReg(SrcReg, false, false, isKill)
|
|
||||||
.addImm(0).addFrameIndex(FI);
|
|
||||||
else
|
|
||||||
assert(0 && "Can't store this register to stack slot");
|
|
||||||
}
|
|
||||||
|
|
||||||
void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
if (RC != Mips::CPURegsRegisterClass)
|
|
||||||
assert(0 && "Can't store this register");
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Mips::SW))
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void MipsRegisterInfo::
|
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned DestReg, int FI,
|
|
||||||
const TargetRegisterClass *RC) const
|
|
||||||
{
|
|
||||||
if (RC == Mips::CPURegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
|
|
||||||
else
|
|
||||||
assert(0 && "Can't load this register from stack slot");
|
|
||||||
}
|
|
||||||
|
|
||||||
void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
if (RC != Mips::CPURegsRegisterClass)
|
|
||||||
assert(0 && "Can't load this register");
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Mips::LW), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
void MipsRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg,
|
unsigned DestReg,
|
||||||
|
|
|
@ -32,26 +32,6 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
@ -65,12 +45,6 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
|
|
||||||
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
||||||
|
|
||||||
const TargetRegisterClass* const*
|
const TargetRegisterClass* const*
|
||||||
|
|
|
@ -12,6 +12,7 @@
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
#include "PPCInstrInfo.h"
|
#include "PPCInstrInfo.h"
|
||||||
|
#include "PPCInstrBuilder.h"
|
||||||
#include "PPCPredicates.h"
|
#include "PPCPredicates.h"
|
||||||
#include "PPCGenInstrInfo.inc"
|
#include "PPCGenInstrInfo.inc"
|
||||||
#include "PPCTargetMachine.h"
|
#include "PPCTargetMachine.h"
|
||||||
|
@ -305,6 +306,235 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void StoreRegToStackSlot(const TargetInstrInfo &TII,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) {
|
||||||
|
if (RC == PPC::GPRCRegisterClass) {
|
||||||
|
if (SrcReg != PPC::LR) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
||||||
|
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
||||||
|
} else {
|
||||||
|
// FIXME: this spills LR immediately to memory in one step. To do this,
|
||||||
|
// we use R11, which we know cannot be used in the prolog/epilog. This is
|
||||||
|
// a hack.
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
||||||
|
.addReg(PPC::R11, false, false, isKill), FrameIdx));
|
||||||
|
}
|
||||||
|
} else if (RC == PPC::G8RCRegisterClass) {
|
||||||
|
if (SrcReg != PPC::LR8) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
|
||||||
|
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
||||||
|
} else {
|
||||||
|
// FIXME: this spills LR immediately to memory in one step. To do this,
|
||||||
|
// we use R11, which we know cannot be used in the prolog/epilog. This is
|
||||||
|
// a hack.
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
|
||||||
|
.addReg(PPC::X11, false, false, isKill), FrameIdx));
|
||||||
|
}
|
||||||
|
} else if (RC == PPC::F8RCRegisterClass) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
|
||||||
|
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
||||||
|
} else if (RC == PPC::F4RCRegisterClass) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
|
||||||
|
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
||||||
|
} else if (RC == PPC::CRRCRegisterClass) {
|
||||||
|
// FIXME: We use R0 here, because it isn't available for RA.
|
||||||
|
// We need to store the CR in the low 4-bits of the saved value. First,
|
||||||
|
// issue a MFCR to save all of the CRBits.
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
|
||||||
|
|
||||||
|
// If the saved register wasn't CR0, shift the bits left so that they are in
|
||||||
|
// CR0's slot.
|
||||||
|
if (SrcReg != PPC::CR0) {
|
||||||
|
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
|
||||||
|
// rlwinm r0, r0, ShiftBits, 0, 31.
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
|
||||||
|
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
|
||||||
|
}
|
||||||
|
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
||||||
|
.addReg(PPC::R0, false, false, isKill), FrameIdx));
|
||||||
|
} else if (RC == PPC::VRRCRegisterClass) {
|
||||||
|
// We don't have indexed addressing for vector loads. Emit:
|
||||||
|
// R0 = ADDI FI#
|
||||||
|
// STVX VAL, 0, R0
|
||||||
|
//
|
||||||
|
// FIXME: We use R0 here, because it isn't available for RA.
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
|
||||||
|
FrameIdx, 0, 0));
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
|
||||||
|
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
SmallVector<MachineInstr*, 4> NewMIs;
|
||||||
|
StoreRegToStackSlot(*this, SrcReg, isKill, FrameIdx, RC, NewMIs);
|
||||||
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
||||||
|
MBB.insert(MI, NewMIs[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
if (Addr[0].isFrameIndex()) {
|
||||||
|
StoreRegToStackSlot(*this, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == PPC::GPRCRegisterClass) {
|
||||||
|
Opc = PPC::STW;
|
||||||
|
} else if (RC == PPC::G8RCRegisterClass) {
|
||||||
|
Opc = PPC::STD;
|
||||||
|
} else if (RC == PPC::F8RCRegisterClass) {
|
||||||
|
Opc = PPC::STFD;
|
||||||
|
} else if (RC == PPC::F4RCRegisterClass) {
|
||||||
|
Opc = PPC::STFS;
|
||||||
|
} else if (RC == PPC::VRRCRegisterClass) {
|
||||||
|
Opc = PPC::STVX;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc))
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) {
|
||||||
|
if (RC == PPC::GPRCRegisterClass) {
|
||||||
|
if (DestReg != PPC::LR) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
|
||||||
|
FrameIdx));
|
||||||
|
} else {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
|
||||||
|
FrameIdx));
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
|
||||||
|
}
|
||||||
|
} else if (RC == PPC::G8RCRegisterClass) {
|
||||||
|
if (DestReg != PPC::LR8) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
|
||||||
|
FrameIdx));
|
||||||
|
} else {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
|
||||||
|
FrameIdx));
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
|
||||||
|
}
|
||||||
|
} else if (RC == PPC::F8RCRegisterClass) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
|
||||||
|
FrameIdx));
|
||||||
|
} else if (RC == PPC::F4RCRegisterClass) {
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
|
||||||
|
FrameIdx));
|
||||||
|
} else if (RC == PPC::CRRCRegisterClass) {
|
||||||
|
// FIXME: We use R0 here, because it isn't available for RA.
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
|
||||||
|
FrameIdx));
|
||||||
|
|
||||||
|
// If the reloaded register isn't CR0, shift the bits right so that they are
|
||||||
|
// in the right CR's slot.
|
||||||
|
if (DestReg != PPC::CR0) {
|
||||||
|
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
|
||||||
|
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
|
||||||
|
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
|
||||||
|
}
|
||||||
|
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
|
||||||
|
} else if (RC == PPC::VRRCRegisterClass) {
|
||||||
|
// We don't have indexed addressing for vector loads. Emit:
|
||||||
|
// R0 = ADDI FI#
|
||||||
|
// Dest = LVX 0, R0
|
||||||
|
//
|
||||||
|
// FIXME: We use R0 here, because it isn't available for RA.
|
||||||
|
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
|
||||||
|
FrameIdx, 0, 0));
|
||||||
|
NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
|
||||||
|
.addReg(PPC::R0));
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void
|
||||||
|
PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
SmallVector<MachineInstr*, 4> NewMIs;
|
||||||
|
LoadRegFromStackSlot(*this, DestReg, FrameIdx, RC, NewMIs);
|
||||||
|
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
||||||
|
MBB.insert(MI, NewMIs[i]);
|
||||||
|
}
|
||||||
|
|
||||||
|
void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
||||||
|
if (Addr[0].isFrameIndex()) {
|
||||||
|
LoadRegFromStackSlot(*this, DestReg, Addr[0].getIndex(), RC, NewMIs);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == PPC::GPRCRegisterClass) {
|
||||||
|
assert(DestReg != PPC::LR && "Can't handle this yet!");
|
||||||
|
Opc = PPC::LWZ;
|
||||||
|
} else if (RC == PPC::G8RCRegisterClass) {
|
||||||
|
assert(DestReg != PPC::LR8 && "Can't handle this yet!");
|
||||||
|
Opc = PPC::LD;
|
||||||
|
} else if (RC == PPC::F8RCRegisterClass) {
|
||||||
|
Opc = PPC::LFD;
|
||||||
|
} else if (RC == PPC::F4RCRegisterClass) {
|
||||||
|
Opc = PPC::LFS;
|
||||||
|
} else if (RC == PPC::VRRCRegisterClass) {
|
||||||
|
Opc = PPC::LVX;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass!");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
||||||
if (MBB.empty()) return false;
|
if (MBB.empty()) return false;
|
||||||
|
|
||||||
|
|
|
@ -103,11 +103,32 @@ public:
|
||||||
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||||
MachineBasicBlock *FBB,
|
MachineBasicBlock *FBB,
|
||||||
const std::vector<MachineOperand> &Cond) const;
|
const std::vector<MachineOperand> &Cond) const;
|
||||||
void copyRegToReg(MachineBasicBlock &MBB,
|
virtual void copyRegToReg(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
||||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||||
};
|
};
|
||||||
|
|
|
@ -104,234 +104,6 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
|
||||||
ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
|
ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void StoreRegToStackSlot(const TargetInstrInfo &TII,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) {
|
|
||||||
if (RC == PPC::GPRCRegisterClass) {
|
|
||||||
if (SrcReg != PPC::LR) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
|
||||||
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
|
||||||
} else {
|
|
||||||
// FIXME: this spills LR immediately to memory in one step. To do this,
|
|
||||||
// we use R11, which we know cannot be used in the prolog/epilog. This is
|
|
||||||
// a hack.
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
|
||||||
.addReg(PPC::R11, false, false, isKill), FrameIdx));
|
|
||||||
}
|
|
||||||
} else if (RC == PPC::G8RCRegisterClass) {
|
|
||||||
if (SrcReg != PPC::LR8) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
|
|
||||||
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
|
||||||
} else {
|
|
||||||
// FIXME: this spills LR immediately to memory in one step. To do this,
|
|
||||||
// we use R11, which we know cannot be used in the prolog/epilog. This is
|
|
||||||
// a hack.
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
|
|
||||||
.addReg(PPC::X11, false, false, isKill), FrameIdx));
|
|
||||||
}
|
|
||||||
} else if (RC == PPC::F8RCRegisterClass) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
|
|
||||||
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
|
||||||
} else if (RC == PPC::F4RCRegisterClass) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
|
|
||||||
.addReg(SrcReg, false, false, isKill), FrameIdx));
|
|
||||||
} else if (RC == PPC::CRRCRegisterClass) {
|
|
||||||
// FIXME: We use R0 here, because it isn't available for RA.
|
|
||||||
// We need to store the CR in the low 4-bits of the saved value. First,
|
|
||||||
// issue a MFCR to save all of the CRBits.
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
|
|
||||||
|
|
||||||
// If the saved register wasn't CR0, shift the bits left so that they are in
|
|
||||||
// CR0's slot.
|
|
||||||
if (SrcReg != PPC::CR0) {
|
|
||||||
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
|
|
||||||
// rlwinm r0, r0, ShiftBits, 0, 31.
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
|
|
||||||
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
|
|
||||||
}
|
|
||||||
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
|
|
||||||
.addReg(PPC::R0, false, false, isKill), FrameIdx));
|
|
||||||
} else if (RC == PPC::VRRCRegisterClass) {
|
|
||||||
// We don't have indexed addressing for vector loads. Emit:
|
|
||||||
// R0 = ADDI FI#
|
|
||||||
// STVX VAL, 0, R0
|
|
||||||
//
|
|
||||||
// FIXME: We use R0 here, because it isn't available for RA.
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
|
|
||||||
FrameIdx, 0, 0));
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
|
|
||||||
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
SmallVector<MachineInstr*, 4> NewMIs;
|
|
||||||
StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs);
|
|
||||||
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
||||||
MBB.insert(MI, NewMIs[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
if (Addr[0].isFrameIndex()) {
|
|
||||||
StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == PPC::GPRCRegisterClass) {
|
|
||||||
Opc = PPC::STW;
|
|
||||||
} else if (RC == PPC::G8RCRegisterClass) {
|
|
||||||
Opc = PPC::STD;
|
|
||||||
} else if (RC == PPC::F8RCRegisterClass) {
|
|
||||||
Opc = PPC::STFD;
|
|
||||||
} else if (RC == PPC::F4RCRegisterClass) {
|
|
||||||
Opc = PPC::STFS;
|
|
||||||
} else if (RC == PPC::VRRCRegisterClass) {
|
|
||||||
Opc = PPC::STVX;
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) {
|
|
||||||
if (RC == PPC::GPRCRegisterClass) {
|
|
||||||
if (DestReg != PPC::LR) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
|
|
||||||
FrameIdx));
|
|
||||||
} else {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
|
|
||||||
FrameIdx));
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
|
|
||||||
}
|
|
||||||
} else if (RC == PPC::G8RCRegisterClass) {
|
|
||||||
if (DestReg != PPC::LR8) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
|
|
||||||
FrameIdx));
|
|
||||||
} else {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
|
|
||||||
FrameIdx));
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
|
|
||||||
}
|
|
||||||
} else if (RC == PPC::F8RCRegisterClass) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
|
|
||||||
FrameIdx));
|
|
||||||
} else if (RC == PPC::F4RCRegisterClass) {
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
|
|
||||||
FrameIdx));
|
|
||||||
} else if (RC == PPC::CRRCRegisterClass) {
|
|
||||||
// FIXME: We use R0 here, because it isn't available for RA.
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
|
|
||||||
FrameIdx));
|
|
||||||
|
|
||||||
// If the reloaded register isn't CR0, shift the bits right so that they are
|
|
||||||
// in the right CR's slot.
|
|
||||||
if (DestReg != PPC::CR0) {
|
|
||||||
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
|
|
||||||
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
|
|
||||||
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
|
|
||||||
}
|
|
||||||
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
|
|
||||||
} else if (RC == PPC::VRRCRegisterClass) {
|
|
||||||
// We don't have indexed addressing for vector loads. Emit:
|
|
||||||
// R0 = ADDI FI#
|
|
||||||
// Dest = LVX 0, R0
|
|
||||||
//
|
|
||||||
// FIXME: We use R0 here, because it isn't available for RA.
|
|
||||||
NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
|
|
||||||
FrameIdx, 0, 0));
|
|
||||||
NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
|
|
||||||
.addReg(PPC::R0));
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
void
|
|
||||||
PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
SmallVector<MachineInstr*, 4> NewMIs;
|
|
||||||
LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs);
|
|
||||||
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
|
|
||||||
MBB.insert(MI, NewMIs[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const{
|
|
||||||
if (Addr[0].isFrameIndex()) {
|
|
||||||
LoadRegFromStackSlot(TII, DestReg, Addr[0].getIndex(), RC, NewMIs);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == PPC::GPRCRegisterClass) {
|
|
||||||
assert(DestReg != PPC::LR && "Can't handle this yet!");
|
|
||||||
Opc = PPC::LWZ;
|
|
||||||
} else if (RC == PPC::G8RCRegisterClass) {
|
|
||||||
assert(DestReg != PPC::LR8 && "Can't handle this yet!");
|
|
||||||
Opc = PPC::LD;
|
|
||||||
} else if (RC == PPC::F8RCRegisterClass) {
|
|
||||||
Opc = PPC::LFD;
|
|
||||||
} else if (RC == PPC::F4RCRegisterClass) {
|
|
||||||
Opc = PPC::LFS;
|
|
||||||
} else if (RC == PPC::VRRCRegisterClass) {
|
|
||||||
Opc = PPC::LVX;
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass!");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg,
|
unsigned DestReg,
|
||||||
|
|
|
@ -35,31 +35,6 @@ public:
|
||||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
|
|
@ -129,3 +129,95 @@ void SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
else
|
else
|
||||||
assert (0 && "Can't copy this register");
|
assert (0 && "Can't copy this register");
|
||||||
}
|
}
|
||||||
|
|
||||||
|
void SparcInstrInfo::
|
||||||
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned SrcReg, bool isKill, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
||||||
|
if (RC == SP::IntRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::STri)).addFrameIndex(FI).addImm(0)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
else if (RC == SP::FPRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::STFri)).addFrameIndex(FI).addImm(0)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
else if (RC == SP::DFPRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
else
|
||||||
|
assert(0 && "Can't store this register to stack slot");
|
||||||
|
}
|
||||||
|
|
||||||
|
void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == SP::IntRegsRegisterClass)
|
||||||
|
Opc = SP::STri;
|
||||||
|
else if (RC == SP::FPRegsRegisterClass)
|
||||||
|
Opc = SP::STFri;
|
||||||
|
else if (RC == SP::DFPRegsRegisterClass)
|
||||||
|
Opc = SP::STDFri;
|
||||||
|
else
|
||||||
|
assert(0 && "Can't load this register");
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc));
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else {
|
||||||
|
assert(MO.isFI());
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
}
|
||||||
|
MIB.addReg(SrcReg, false, false, isKill);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
void SparcInstrInfo::
|
||||||
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
|
unsigned DestReg, int FI,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
if (RC == SP::IntRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
|
||||||
|
else if (RC == SP::FPRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
|
||||||
|
else if (RC == SP::DFPRegsRegisterClass)
|
||||||
|
BuildMI(MBB, I, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
|
||||||
|
else
|
||||||
|
assert(0 && "Can't load this register from stack slot");
|
||||||
|
}
|
||||||
|
|
||||||
|
void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == SP::IntRegsRegisterClass)
|
||||||
|
Opc = SP::LDri;
|
||||||
|
else if (RC == SP::FPRegsRegisterClass)
|
||||||
|
Opc = SP::LDFri;
|
||||||
|
else if (RC == SP::DFPRegsRegisterClass)
|
||||||
|
Opc = SP::LDDFri;
|
||||||
|
else
|
||||||
|
assert(0 && "Can't load this register");
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
||||||
|
MachineOperand &MO = Addr[i];
|
||||||
|
if (MO.isReg())
|
||||||
|
MIB.addReg(MO.getReg());
|
||||||
|
else if (MO.isImm())
|
||||||
|
MIB.addImm(MO.getImm());
|
||||||
|
else {
|
||||||
|
assert(MO.isFI());
|
||||||
|
MIB.addFrameIndex(MO.getIndex());
|
||||||
|
}
|
||||||
|
}
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
|
@ -73,6 +73,26 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MBBI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
};
|
};
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -30,98 +30,6 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
|
||||||
Subtarget(st), TII(tii) {
|
Subtarget(st), TII(tii) {
|
||||||
}
|
}
|
||||||
|
|
||||||
void SparcRegisterInfo::
|
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned SrcReg, bool isKill, int FI,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
|
||||||
if (RC == SP::IntRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
else if (RC == SP::FPRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
else if (RC == SP::DFPRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
else
|
|
||||||
assert(0 && "Can't store this register to stack slot");
|
|
||||||
}
|
|
||||||
|
|
||||||
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == SP::IntRegsRegisterClass)
|
|
||||||
Opc = SP::STri;
|
|
||||||
else if (RC == SP::FPRegsRegisterClass)
|
|
||||||
Opc = SP::STFri;
|
|
||||||
else if (RC == SP::DFPRegsRegisterClass)
|
|
||||||
Opc = SP::STDFri;
|
|
||||||
else
|
|
||||||
assert(0 && "Can't load this register");
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isRegister())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImmediate())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else {
|
|
||||||
assert(MO.isFI());
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
}
|
|
||||||
MIB.addReg(SrcReg, false, false, isKill);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void SparcRegisterInfo::
|
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|
||||||
unsigned DestReg, int FI,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
if (RC == SP::IntRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
|
|
||||||
else if (RC == SP::FPRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
|
|
||||||
else if (RC == SP::DFPRegsRegisterClass)
|
|
||||||
BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
|
|
||||||
else
|
|
||||||
assert(0 && "Can't load this register from stack slot");
|
|
||||||
}
|
|
||||||
|
|
||||||
void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == SP::IntRegsRegisterClass)
|
|
||||||
Opc = SP::LDri;
|
|
||||||
else if (RC == SP::FPRegsRegisterClass)
|
|
||||||
Opc = SP::LDFri;
|
|
||||||
else if (RC == SP::DFPRegsRegisterClass)
|
|
||||||
Opc = SP::LDDFri;
|
|
||||||
else
|
|
||||||
assert(0 && "Can't load this register");
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
|
|
||||||
MachineOperand &MO = Addr[i];
|
|
||||||
if (MO.isReg())
|
|
||||||
MIB.addReg(MO.getReg());
|
|
||||||
else if (MO.isImm())
|
|
||||||
MIB.addImm(MO.getImm());
|
|
||||||
else {
|
|
||||||
assert(MO.isFI());
|
|
||||||
MIB.addFrameIndex(MO.getIndex());
|
|
||||||
}
|
|
||||||
}
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator I,
|
MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg,
|
unsigned DestReg,
|
||||||
|
|
|
@ -29,32 +29,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
||||||
|
|
||||||
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
|
SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
|
||||||
|
|
||||||
/// Code Generation virtual methods...
|
/// Code Generation virtual methods...
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
|
||||||
unsigned DestReg, const MachineInstr *Orig) const;
|
unsigned DestReg, const MachineInstr *Orig) const;
|
||||||
|
|
||||||
|
|
|
@ -756,6 +756,29 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
||||||
return 2;
|
return 2;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
|
||||||
|
MachineOperand &MO) {
|
||||||
|
if (MO.isRegister())
|
||||||
|
MIB = MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit(),
|
||||||
|
false, false, MO.getSubReg());
|
||||||
|
else if (MO.isImmediate())
|
||||||
|
MIB = MIB.addImm(MO.getImm());
|
||||||
|
else if (MO.isFrameIndex())
|
||||||
|
MIB = MIB.addFrameIndex(MO.getIndex());
|
||||||
|
else if (MO.isGlobalAddress())
|
||||||
|
MIB = MIB.addGlobalAddress(MO.getGlobal(), MO.getOffset());
|
||||||
|
else if (MO.isConstantPoolIndex())
|
||||||
|
MIB = MIB.addConstantPoolIndex(MO.getIndex(), MO.getOffset());
|
||||||
|
else if (MO.isJumpTableIndex())
|
||||||
|
MIB = MIB.addJumpTableIndex(MO.getIndex());
|
||||||
|
else if (MO.isExternalSymbol())
|
||||||
|
MIB = MIB.addExternalSymbol(MO.getSymbolName());
|
||||||
|
else
|
||||||
|
assert(0 && "Unknown operand for X86InstrAddOperand!");
|
||||||
|
|
||||||
|
return MIB;
|
||||||
|
}
|
||||||
|
|
||||||
unsigned
|
unsigned
|
||||||
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
||||||
MachineBasicBlock *FBB,
|
MachineBasicBlock *FBB,
|
||||||
|
@ -852,6 +875,125 @@ void X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||||
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
|
BuildMI(MBB, MI, get(Opc), DestReg).addReg(SrcReg);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
|
||||||
|
unsigned StackAlign) {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == &X86::GR64RegClass) {
|
||||||
|
Opc = X86::MOV64mr;
|
||||||
|
} else if (RC == &X86::GR32RegClass) {
|
||||||
|
Opc = X86::MOV32mr;
|
||||||
|
} else if (RC == &X86::GR16RegClass) {
|
||||||
|
Opc = X86::MOV16mr;
|
||||||
|
} else if (RC == &X86::GR8RegClass) {
|
||||||
|
Opc = X86::MOV8mr;
|
||||||
|
} else if (RC == &X86::GR32_RegClass) {
|
||||||
|
Opc = X86::MOV32_mr;
|
||||||
|
} else if (RC == &X86::GR16_RegClass) {
|
||||||
|
Opc = X86::MOV16_mr;
|
||||||
|
} else if (RC == &X86::RFP80RegClass) {
|
||||||
|
Opc = X86::ST_FpP80m; // pops
|
||||||
|
} else if (RC == &X86::RFP64RegClass) {
|
||||||
|
Opc = X86::ST_Fp64m;
|
||||||
|
} else if (RC == &X86::RFP32RegClass) {
|
||||||
|
Opc = X86::ST_Fp32m;
|
||||||
|
} else if (RC == &X86::FR32RegClass) {
|
||||||
|
Opc = X86::MOVSSmr;
|
||||||
|
} else if (RC == &X86::FR64RegClass) {
|
||||||
|
Opc = X86::MOVSDmr;
|
||||||
|
} else if (RC == &X86::VR128RegClass) {
|
||||||
|
// FIXME: Use movaps once we are capable of selectively
|
||||||
|
// aligning functions that spill SSE registers on 16-byte boundaries.
|
||||||
|
Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
|
||||||
|
} else if (RC == &X86::VR64RegClass) {
|
||||||
|
Opc = X86::MMX_MOVQ64mr;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
return Opc;
|
||||||
|
}
|
||||||
|
|
||||||
|
void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const {
|
||||||
|
unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
|
||||||
|
addFrameReference(BuildMI(MBB, MI, get(Opc)), FrameIdx)
|
||||||
|
.addReg(SrcReg, false, false, isKill);
|
||||||
|
}
|
||||||
|
|
||||||
|
void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||||
|
bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = getStoreRegOpcode(RC, RI.getStackAlignment());
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc));
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = X86InstrAddOperand(MIB, Addr[i]);
|
||||||
|
MIB.addReg(SrcReg, false, false, isKill);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
|
||||||
|
static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
|
||||||
|
unsigned StackAlign) {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == &X86::GR64RegClass) {
|
||||||
|
Opc = X86::MOV64rm;
|
||||||
|
} else if (RC == &X86::GR32RegClass) {
|
||||||
|
Opc = X86::MOV32rm;
|
||||||
|
} else if (RC == &X86::GR16RegClass) {
|
||||||
|
Opc = X86::MOV16rm;
|
||||||
|
} else if (RC == &X86::GR8RegClass) {
|
||||||
|
Opc = X86::MOV8rm;
|
||||||
|
} else if (RC == &X86::GR32_RegClass) {
|
||||||
|
Opc = X86::MOV32_rm;
|
||||||
|
} else if (RC == &X86::GR16_RegClass) {
|
||||||
|
Opc = X86::MOV16_rm;
|
||||||
|
} else if (RC == &X86::RFP80RegClass) {
|
||||||
|
Opc = X86::LD_Fp80m;
|
||||||
|
} else if (RC == &X86::RFP64RegClass) {
|
||||||
|
Opc = X86::LD_Fp64m;
|
||||||
|
} else if (RC == &X86::RFP32RegClass) {
|
||||||
|
Opc = X86::LD_Fp32m;
|
||||||
|
} else if (RC == &X86::FR32RegClass) {
|
||||||
|
Opc = X86::MOVSSrm;
|
||||||
|
} else if (RC == &X86::FR64RegClass) {
|
||||||
|
Opc = X86::MOVSDrm;
|
||||||
|
} else if (RC == &X86::VR128RegClass) {
|
||||||
|
// FIXME: Use movaps once we are capable of selectively
|
||||||
|
// aligning functions that spill SSE registers on 16-byte boundaries.
|
||||||
|
Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
|
||||||
|
} else if (RC == &X86::VR64RegClass) {
|
||||||
|
Opc = X86::MMX_MOVQ64rm;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
return Opc;
|
||||||
|
}
|
||||||
|
|
||||||
|
void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIdx,
|
||||||
|
const TargetRegisterClass *RC) const{
|
||||||
|
unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
|
||||||
|
addFrameReference(BuildMI(MBB, MI, get(Opc), DestReg), FrameIdx);
|
||||||
|
}
|
||||||
|
|
||||||
|
void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||||
|
unsigned Opc = getLoadRegOpcode(RC, RI.getStackAlignment());
|
||||||
|
MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
|
||||||
|
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
||||||
|
MIB = X86InstrAddOperand(MIB, Addr[i]);
|
||||||
|
NewMIs.push_back(MIB);
|
||||||
|
}
|
||||||
|
|
||||||
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
|
||||||
if (MBB.empty()) return false;
|
if (MBB.empty()) return false;
|
||||||
|
|
||||||
|
|
|
@ -284,6 +284,25 @@ public:
|
||||||
unsigned DestReg, unsigned SrcReg,
|
unsigned DestReg, unsigned SrcReg,
|
||||||
const TargetRegisterClass *DestRC,
|
const TargetRegisterClass *DestRC,
|
||||||
const TargetRegisterClass *SrcRC) const;
|
const TargetRegisterClass *SrcRC) const;
|
||||||
|
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned SrcReg, bool isKill, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||||
|
MachineBasicBlock::iterator MI,
|
||||||
|
unsigned DestReg, int FrameIndex,
|
||||||
|
const TargetRegisterClass *RC) const;
|
||||||
|
|
||||||
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||||
|
SmallVectorImpl<MachineOperand> &Addr,
|
||||||
|
const TargetRegisterClass *RC,
|
||||||
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||||
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
|
||||||
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
|
||||||
|
|
||||||
|
|
|
@ -836,86 +836,6 @@ static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
|
||||||
return Opc;
|
return Opc;
|
||||||
}
|
}
|
||||||
|
|
||||||
void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const {
|
|
||||||
unsigned Opc = getStoreRegOpcode(RC, StackAlign);
|
|
||||||
addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
|
|
||||||
.addReg(SrcReg, false, false, isKill);
|
|
||||||
}
|
|
||||||
|
|
||||||
void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
|
||||||
bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = getStoreRegOpcode(RC, StackAlign);
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = X86InstrAddOperand(MIB, Addr[i]);
|
|
||||||
MIB.addReg(SrcReg, false, false, isKill);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
|
|
||||||
static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
|
|
||||||
unsigned StackAlign) {
|
|
||||||
unsigned Opc = 0;
|
|
||||||
if (RC == &X86::GR64RegClass) {
|
|
||||||
Opc = X86::MOV64rm;
|
|
||||||
} else if (RC == &X86::GR32RegClass) {
|
|
||||||
Opc = X86::MOV32rm;
|
|
||||||
} else if (RC == &X86::GR16RegClass) {
|
|
||||||
Opc = X86::MOV16rm;
|
|
||||||
} else if (RC == &X86::GR8RegClass) {
|
|
||||||
Opc = X86::MOV8rm;
|
|
||||||
} else if (RC == &X86::GR32_RegClass) {
|
|
||||||
Opc = X86::MOV32_rm;
|
|
||||||
} else if (RC == &X86::GR16_RegClass) {
|
|
||||||
Opc = X86::MOV16_rm;
|
|
||||||
} else if (RC == &X86::RFP80RegClass) {
|
|
||||||
Opc = X86::LD_Fp80m;
|
|
||||||
} else if (RC == &X86::RFP64RegClass) {
|
|
||||||
Opc = X86::LD_Fp64m;
|
|
||||||
} else if (RC == &X86::RFP32RegClass) {
|
|
||||||
Opc = X86::LD_Fp32m;
|
|
||||||
} else if (RC == &X86::FR32RegClass) {
|
|
||||||
Opc = X86::MOVSSrm;
|
|
||||||
} else if (RC == &X86::FR64RegClass) {
|
|
||||||
Opc = X86::MOVSDrm;
|
|
||||||
} else if (RC == &X86::VR128RegClass) {
|
|
||||||
// FIXME: Use movaps once we are capable of selectively
|
|
||||||
// aligning functions that spill SSE registers on 16-byte boundaries.
|
|
||||||
Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
|
|
||||||
} else if (RC == &X86::VR64RegClass) {
|
|
||||||
Opc = X86::MMX_MOVQ64rm;
|
|
||||||
} else {
|
|
||||||
assert(0 && "Unknown regclass");
|
|
||||||
abort();
|
|
||||||
}
|
|
||||||
|
|
||||||
return Opc;
|
|
||||||
}
|
|
||||||
|
|
||||||
void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIdx,
|
|
||||||
const TargetRegisterClass *RC) const{
|
|
||||||
unsigned Opc = getLoadRegOpcode(RC, StackAlign);
|
|
||||||
addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
|
|
||||||
}
|
|
||||||
|
|
||||||
void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
|
||||||
unsigned Opc = getLoadRegOpcode(RC, StackAlign);
|
|
||||||
MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
|
|
||||||
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
|
|
||||||
MIB = X86InstrAddOperand(MIB, Addr[i]);
|
|
||||||
NewMIs.push_back(MIB);
|
|
||||||
}
|
|
||||||
|
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
|
||||||
if (RC == &X86::CCRRegClass)
|
if (RC == &X86::CCRRegClass)
|
||||||
|
@ -1229,7 +1149,7 @@ bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
||||||
|
|
||||||
// Emit the load instruction.
|
// Emit the load instruction.
|
||||||
if (UnfoldLoad) {
|
if (UnfoldLoad) {
|
||||||
loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
|
TII.loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs);
|
||||||
if (UnfoldStore) {
|
if (UnfoldStore) {
|
||||||
// Address operands cannot be marked isKill.
|
// Address operands cannot be marked isKill.
|
||||||
for (unsigned i = 1; i != 5; ++i) {
|
for (unsigned i = 1; i != 5; ++i) {
|
||||||
|
@ -1286,12 +1206,50 @@ bool X86RegisterInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
||||||
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
|
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
|
||||||
const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
|
const TargetRegisterClass *DstRC = (DstTOI.Flags & M_LOOK_UP_PTR_REG_CLASS)
|
||||||
? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
|
? TII.getPointerRegClass() : getRegClass(DstTOI.RegClass);
|
||||||
storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
|
TII.storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs);
|
||||||
}
|
}
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
|
||||||
|
unsigned StackAlign) {
|
||||||
|
unsigned Opc = 0;
|
||||||
|
if (RC == &X86::GR64RegClass) {
|
||||||
|
Opc = X86::MOV64rm;
|
||||||
|
} else if (RC == &X86::GR32RegClass) {
|
||||||
|
Opc = X86::MOV32rm;
|
||||||
|
} else if (RC == &X86::GR16RegClass) {
|
||||||
|
Opc = X86::MOV16rm;
|
||||||
|
} else if (RC == &X86::GR8RegClass) {
|
||||||
|
Opc = X86::MOV8rm;
|
||||||
|
} else if (RC == &X86::GR32_RegClass) {
|
||||||
|
Opc = X86::MOV32_rm;
|
||||||
|
} else if (RC == &X86::GR16_RegClass) {
|
||||||
|
Opc = X86::MOV16_rm;
|
||||||
|
} else if (RC == &X86::RFP80RegClass) {
|
||||||
|
Opc = X86::LD_Fp80m;
|
||||||
|
} else if (RC == &X86::RFP64RegClass) {
|
||||||
|
Opc = X86::LD_Fp64m;
|
||||||
|
} else if (RC == &X86::RFP32RegClass) {
|
||||||
|
Opc = X86::LD_Fp32m;
|
||||||
|
} else if (RC == &X86::FR32RegClass) {
|
||||||
|
Opc = X86::MOVSSrm;
|
||||||
|
} else if (RC == &X86::FR64RegClass) {
|
||||||
|
Opc = X86::MOVSDrm;
|
||||||
|
} else if (RC == &X86::VR128RegClass) {
|
||||||
|
// FIXME: Use movaps once we are capable of selectively
|
||||||
|
// aligning functions that spill SSE registers on 16-byte boundaries.
|
||||||
|
Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
|
||||||
|
} else if (RC == &X86::VR64RegClass) {
|
||||||
|
Opc = X86::MMX_MOVQ64rm;
|
||||||
|
} else {
|
||||||
|
assert(0 && "Unknown regclass");
|
||||||
|
abort();
|
||||||
|
}
|
||||||
|
|
||||||
|
return Opc;
|
||||||
|
}
|
||||||
|
|
||||||
bool
|
bool
|
||||||
X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
||||||
|
|
|
@ -85,6 +85,8 @@ public:
|
||||||
/// register identifier.
|
/// register identifier.
|
||||||
unsigned getX86RegNum(unsigned RegNo);
|
unsigned getX86RegNum(unsigned RegNo);
|
||||||
|
|
||||||
|
unsigned getStackAlignment() const { return StackAlign; }
|
||||||
|
|
||||||
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
|
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
|
||||||
/// (created by TableGen) for target dependencies.
|
/// (created by TableGen) for target dependencies.
|
||||||
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
||||||
|
@ -98,32 +100,6 @@ public:
|
||||||
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
|
||||||
MachineBasicBlock::iterator MI,
|
MachineBasicBlock::iterator MI,
|
||||||
const std::vector<CalleeSavedInfo> &CSI) const;
|
const std::vector<CalleeSavedInfo> &CSI) const;
|
||||||
|
|
||||||
void storeRegToStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned SrcReg, bool isKill, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, int FrameIndex,
|
|
||||||
const TargetRegisterClass *RC) const;
|
|
||||||
|
|
||||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
||||||
SmallVectorImpl<MachineOperand> &Addr,
|
|
||||||
const TargetRegisterClass *RC,
|
|
||||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
||||||
|
|
||||||
void copyRegToReg(MachineBasicBlock &MBB,
|
|
||||||
MachineBasicBlock::iterator MI,
|
|
||||||
unsigned DestReg, unsigned SrcReg,
|
|
||||||
const TargetRegisterClass *DestRC,
|
|
||||||
const TargetRegisterClass *SrcRC) const;
|
|
||||||
|
|
||||||
const TargetRegisterClass *
|
const TargetRegisterClass *
|
||||||
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
|
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
|
||||||
|
|
Loading…
Reference in New Issue