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[mips] Move conditional moves out of isCodeGenOnly 

Reviewers: atanasyan, smaksimovic, abeserminji

Differential Revision: https://reviews.llvm.org/D46389

llvm-svn: 331863
This commit is contained in:
Simon Dardis 2018-05-09 10:33:21 +00:00
parent 9a85470a57
commit eead208872
6 changed files with 62 additions and 28 deletions
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46
llvm/lib/Target/Mips/MicroMipsInstrFPU.td
View File

@ -163,32 +163,34 @@ def CVT_S_W_MM : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
defm FNEG : ABSS_MMM<"neg.d", II_NEG, fneg>, ABS_FM_MM<1, 0x2d>;
defm FMOV : ABSS_MMM<"mov.d", II_MOV_D>, ABS_FM_MM<1, 0x1>;
let isCodeGenOnly = 1 in {
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
let DecoderNamespace = "MicroMips" in {
def MOVZ_I_S_MM : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd,
II_MOVZ_S>, CMov_I_F_FM_MM<0x78, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVN_I_S_MM : MMRel, CMov_I_F_FT<"movn.s", GPR32Opnd, FGR32Opnd,
II_MOVN_S>, CMov_I_F_FM_MM<0x38, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVZ_I_D32_MM : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
II_MOVZ_D>, CMov_I_F_FM_MM<0x78, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVN_I_D32_MM : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM_MM<0x38, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
def MOVT_S_MM : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVF_S_MM : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 0>,
ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
let isCodeGenOnly = 1 in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS;

4
llvm/lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -831,13 +831,13 @@ class ABS_FM_MM<bits<2> fmt, bits<7> funct> : MMArch {
class CMov_F_F_FM_MM<bits<9> func, bits<2> fmt> : MMArch {
bits<5> fd;
bits<5> fs;
bits<3> fcc;
bits<32> Inst;
let Inst{31-26} = 0x15;
let Inst{25-21} = fd;
let Inst{20-16} = fs;
let Inst{15-13} = 0x0; //cc
let Inst{15-13} = fcc; //cc
let Inst{12-11} = 0x0;
let Inst{10-9} = fmt;
let Inst{8-0} = func;

8
llvm/lib/Target/Mips/MipsCondMov.td
View File

@ -127,7 +127,7 @@ let isCodeGenOnly = 1 in {
def MOVN_I64_I64 : CMov_I_I_FT<"movn", GPR64Opnd, GPR64Opnd, II_MOVN>,
ADD_FM<0, 0xb>, INSN_MIPS4_32_NOT_32R6_64R6;
}
let AdditionalPredicates = [NotInMicroMips] in {
def MOVZ_I_S : MMRel, CMov_I_F_FT<"movz.s", GPR32Opnd, FGR32Opnd, II_MOVZ_S>,
CMov_I_F_FM<18, 16>, INSN_MIPS4_32_NOT_32R6_64R6;
@ -148,7 +148,7 @@ def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
II_MOVN_D>, CMov_I_F_FM<19, 17>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace = "MipsFP64" in {
def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
CMov_I_F_FM<18, 17>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;
@ -175,7 +175,7 @@ def MOVF_I : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
let isCodeGenOnly = 1 in
def MOVF_I64 : CMov_F_I_FT<"movf", GPR64Opnd, II_MOVF, MipsCMovFP_F>,
CMov_F_I_FM<0>, INSN_MIPS4_32_NOT_32R6_64R6, GPR_64;
let AdditionalPredicates = [NotInMicroMips] in {
def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
CMov_F_F_FM<16, 1>, INSN_MIPS4_32_NOT_32R6_64R6;
def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
@ -187,7 +187,7 @@ def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM<17, 0>,
INSN_MIPS4_32_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace = "MipsFP64" in {
def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
CMov_F_F_FM<17, 1>, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64;

8
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
View File

@ -111,6 +111,14 @@
0xe6 0x00 0x18 0x48 # CHECK: movn $9, $6, $7
0x26 0x55 0x7b 0x09 # CHECK: movt $9, $6, $fcc0
0x26 0x55 0x7b 0x01 # CHECK: movf $9, $6, $fcc0
0xe6 0x54 0x78 0x20 # CHECK: movz.s $f4, $f6, $7
0xe6 0x54 0x78 0x21 # CHECK: movz.d $f4, $f6, $7
0xe6 0x54 0x38 0x20 # CHECK: movn.s $f4, $f6, $7
0xe6 0x54 0x38 0x21 # CHECK: movn.d $f4, $f6, $7
0x86 0x54 0x60 0x00 # CHECK: movt.s $f4, $f6, $fcc0
0x86 0x54 0x60 0x02 # CHECK: movt.d $f4, $f6, $fcc0
0x86 0x54 0x20 0x00 # CHECK: movf.s $f4, $f6, $fcc0
0x86 0x54 0x20 0x02 # CHECK: movf.d $f4, $f6, $fcc0
0x06 0x00 0x7c 0x2d # CHECK: mthi $6
0x06 0x00 0x7c 0x0d # CHECK: mfhi $6
0x06 0x00 0x7c 0x3d # CHECK: mtlo $6

8
llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
View File

@ -111,6 +111,14 @@
0x00 0xe6 0x48 0x18 # CHECK: movn $9, $6, $7
0x55 0x26 0x09 0x7b # CHECK: movt $9, $6, $fcc0
0x55 0x26 0x01 0x7b # CHECK: movf $9, $6, $fcc0
0x54 0xe6 0x20 0x78 # CHECK: movz.s $f4, $f6, $7
0x54 0xe6 0x21 0x78 # CHECK: movz.d $f4, $f6, $7
0x54 0xe6 0x20 0x38 # CHECK: movn.s $f4, $f6, $7
0x54 0xe6 0x21 0x38 # CHECK: movn.d $f4, $f6, $7
0x54 0x86 0x00 0x60 # CHECK: movt.s $f4, $f6, $fcc0
0x54 0x86 0x02 0x60 # CHECK: movt.d $f4, $f6, $fcc0
0x54 0x86 0x00 0x20 # CHECK: movf.s $f4, $f6, $fcc0
0x54 0x86 0x02 0x20 # CHECK: movf.d $f4, $f6, $fcc0
0x00 0x06 0x2d 0x7c # CHECK: mthi $6
0x00 0x06 0x0d 0x7c # CHECK: mfhi $6
0x00 0x06 0x3d 0x7c # CHECK: mtlo $6

16
llvm/test/MC/Mips/micromips-fpu-instructions.s
View File

@ -57,13 +57,21 @@
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EL: movn.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EL: movn.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x38,0x21]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
# CHECK-EL: movt.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x00]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
# CHECK-EL: movt.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x60,0x02]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM
# CHECK-EL: movf.s $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x00]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
# CHECK-EL: movf.d $f4, $f6, $fcc0 # encoding: [0x86,0x54,0x20,0x02]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EL: madd.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x01,0x11]
# CHECK-EL: madd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x09,0x11]
# CHECK-EL: msub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x21,0x11]
@ -123,13 +131,21 @@
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_D32_MM
# CHECK-EB: movn.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_S_MM
# CHECK-EB: movn.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x38]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVN_I_D32_MM
# CHECK-EB: movt.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x60]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
# CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM
# CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]