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Duplicated node may produce a non-physical register def. 

llvm-svn: 62015
This commit is contained in:
Evan Cheng 2009-01-09 22:44:02 +00:00
parent 658b9550bb
commit ed74d8ac2a
3 changed files with 47 additions and 4 deletions
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2
llvm/include/llvm/CodeGen/ScheduleDAGSDNodes.h
View File

@ -188,7 +188,7 @@ namespace llvm {
DenseMap<SDValue, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
const TargetInstrDesc &II, bool IsClone,
DenseMap<SDValue, unsigned> &VRBaseMap);
/// BuildSchedUnits, AddSchedEdges - Helper functions for BuildSchedGraph.

8
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
View File

@ -157,8 +157,8 @@ unsigned ScheduleDAGSDNodes::getDstOfOnlyCopyToRegUse(SDNode *Node,
}
void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
DenseMap<SDValue, unsigned> &VRBaseMap) {
const TargetInstrDesc &II, bool IsClone,
DenseMap<SDValue, unsigned> &VRBaseMap) {
assert(Node->getMachineOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
@ -192,6 +192,8 @@ void ScheduleDAGSDNodes::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
}
SDValue Op(Node, i);
if (IsClone)
VRBaseMap.erase(Op);
bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
isNew = isNew; // Silence compiler warning.
assert(isNew && "Node emitted out of order - early");
@ -487,7 +489,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone,
// Add result register values for things that are defined by this
// instruction.
if (NumResults)
CreateVirtualRegisters(Node, MI, II, VRBaseMap);
CreateVirtualRegisters(Node, MI, II, IsClone, VRBaseMap);
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.

41
llvm/test/CodeGen/X86/2009-01-09-SchedDupBug.ll Normal file
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@ -0,0 +1,41 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
; rdar://6481994
%Value = type { i32 (...)** }
declare { i32, i1 } @llvm.sadd.with.overflow.i32(i32, i32) nounwind
define %Value* @bar(%Value** %exception) nounwind {
prologue:
br i1 true, label %NextVerify41, label %FailedVerify
NextVerify41: ; preds = %prologue
br i1 true, label %NextVerify, label %FailedVerify
NextVerify: ; preds = %NextVerify41
br i1 false, label %label12, label %label
label: ; preds = %NextVerify
br i1 true, label %xxNumberLiteral.exit, label %handle_exception
xxNumberLiteral.exit: ; preds = %label
%0 = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 0, i32 0) ; <{ i32, i1 }> [#uses=2]
%intAdd = extractvalue { i32, i1 } %0, 0 ; <i32> [#uses=1]
%intAddOverflow = extractvalue { i32, i1 } %0, 1 ; <i1> [#uses=1]
%toint55 = ashr i32 %intAdd, 1 ; <i32> [#uses=1]
%toFP56 = sitofp i32 %toint55 to double ; <double> [#uses=1]
br i1 %intAddOverflow, label %exit, label %label12
label12: ; preds = %xxNumberLiteral.exit, %NextVerify
%var_lr1.0 = phi double [ %toFP56, %xxNumberLiteral.exit ], [ 0.000000e+00, %NextVerify ] ; <double> [#uses=0]
unreachable
exit: ; preds = %xxNumberLiteral.exit
ret %Value* null
FailedVerify: ; preds = %NextVerify41, %prologue
ret %Value* null
handle_exception: ; preds = %label
ret %Value* undef
}