[mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this pattern is matched: (select (setgt a, Constant), T, F) The pattern above effectively turns into this: (conditional-move (setlt a, Constant + 1), F, T) llvm-svn: 176384
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@ -68,6 +68,13 @@ multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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(MOVZInst DRC:$T, (SLTOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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def : MipsPat<(select (i32 (setule CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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(MOVZInst DRC:$T, (SLTuOp CRC:$rhs, CRC:$lhs), DRC:$F)>;
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def : MipsPat<(select (i32 (setgt CRC:$lhs, immSExt16Plus1:$rhs)),
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DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiOp CRC:$lhs, (Plus1 imm:$rhs)), DRC:$F)>;
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def : MipsPat<(select (i32 (setugt CRC:$lhs, immSExt16Plus1:$rhs)),
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DRC:$T, DRC:$F),
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(MOVZInst DRC:$T, (SLTiuOp CRC:$lhs, (Plus1 imm:$rhs)),
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DRC:$F)>;
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}
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}
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multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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multiclass MovzPats1<RegisterClass CRC, RegisterClass DRC,
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@ -109,7 +109,7 @@ private:
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SDValue &Alias);
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SDValue &Alias);
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// getImm - Return a target constant with the specified value.
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// getImm - Return a target constant with the specified value.
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inline SDValue getImm(const SDNode *Node, unsigned Imm) {
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inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
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}
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}
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@ -299,6 +299,9 @@ def HI16 : SDNodeXForm<imm, [{
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return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
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return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
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}]>;
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}]>;
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// Plus 1.
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def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
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// Node immediate fits as 16-bit sign extended on target immediate.
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// Node immediate fits as 16-bit sign extended on target immediate.
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// e.g. addi, andi
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// e.g. addi, andi
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def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
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def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
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@ -331,6 +334,11 @@ def immLow16Zero : PatLeaf<(imm), [{
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// shamt field must fit in 5 bits.
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// shamt field must fit in 5 bits.
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def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
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// True if (N + 1) fits in 16-bit field.
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def immSExt16Plus1 : PatLeaf<(imm), [{
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return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
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}]>;
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// Mips Address Mode! SDNode frameindex could possibily be a match
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// since load and store instructions from stack used it.
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// since load and store instructions from stack used it.
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def addr :
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def addr :
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@ -59,3 +59,140 @@ entry:
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ret i64 %cond
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ret i64 %cond
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}
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}
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; slti and conditional move.
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;
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; Check that, pattern
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; (select (setgt a, N), t, f)
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; turns into
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; (movz t, (setlt a, N + 1), f)
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; if N + 1 fits in 16-bit.
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; O32: slti0:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti0(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti1:
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; O32: slt ${{[0-9]+}}
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define i32 @slti1(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti2:
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; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @slti2(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: slti3:
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; O32: slt ${{[0-9]+}}
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define i32 @slti3(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; 64-bit patterns.
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; N64: slti64_0:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_0(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32766
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_1:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_1(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, 32767
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_2:
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; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i64 @slti64_2(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32769
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; N64: slti64_3:
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; N64: slt ${{[0-9]+}}
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define i64 @slti64_3(i64 %a) {
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entry:
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%cmp = icmp sgt i64 %a, -32770
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%conv = select i1 %cmp, i64 3, i64 4
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ret i64 %conv
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}
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; sltiu instructions.
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; O32: sltiu0:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu0(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32766
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu1:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu1(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, 32767
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu2:
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; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
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; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
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define i32 @sltiu2(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32769
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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; O32: sltiu3:
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; O32: sltu ${{[0-9]+}}
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define i32 @sltiu3(i32 %a) {
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entry:
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%cmp = icmp ugt i32 %a, -32770
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%cond = select i1 %cmp, i32 3, i32 4
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ret i32 %cond
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}
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@ -632,9 +632,9 @@ entry:
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; CHECK: or $[[R3:[0-9]+]], $8, $zero
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; CHECK: or $[[R3:[0-9]+]], $8, $zero
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; CHECK: ld $25, %call16(__gttf2)($gp)
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; CHECK: ld $25, %call16(__gttf2)($gp)
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; CHECK: jalr $25
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; CHECK: jalr $25
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; CHECK: slt $1, $zero, $2
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; CHECK: slti $1, $2, 1
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; CHECK: movn $[[R1]], $[[R3]], $1
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; CHECK: movz $[[R1]], $[[R3]], $1
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; CHECK: movn $[[R0]], $[[R2]], $1
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; CHECK: movz $[[R0]], $[[R2]], $1
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; CHECK: or $2, $[[R1]], $zero
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; CHECK: or $2, $[[R1]], $zero
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; CHECK: or $3, $[[R0]], $zero
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; CHECK: or $3, $[[R0]], $zero
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