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Remove isImplicitDef TargetInstrDesc flag. 

llvm-svn: 48381
This commit is contained in:
Evan Cheng 2008-03-15 00:19:36 +00:00
parent 0e7b00d79f
commit ec7533b620
6 changed files with 3 additions and 16 deletions
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8
llvm/include/llvm/Target/TargetInstrDesc.h
View File

@ -81,7 +81,6 @@ namespace TID {
HasOptionalDef,
Return,
Call,
ImplicitDef,
Barrier,
Terminator,
Branch,
@ -219,13 +218,6 @@ public:
return Flags & (1 << TID::Call);
}
/// isImplicitDef - Return true if this is an "IMPLICIT_DEF" instruction,
/// which defines a register to an unspecified value. These basically
/// correspond to x = undef.
bool isImplicitDef() const {
return Flags & (1 << TID::ImplicitDef);
}
/// isBarrier - Returns true if the specified instruction stops control flow
/// from executing the instruction immediately following it. Examples include
/// unconditional branches and return instructions.

7
llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -641,8 +641,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
return false;
isLoad = false;
const TargetInstrDesc &TID = MI->getDesc();
if (TID.isImplicitDef())
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return true;
int FrameIdx = 0;
@ -655,6 +654,7 @@ bool LiveIntervals::isReMaterializable(const LiveInterval &li,
return true;
if (tii_->isTriviallyReMaterializable(MI)) {
const TargetInstrDesc &TID = MI->getDesc();
isLoad = TID.isSimpleLoad();
unsigned ImpUse = getReMatImplicitUse(li, MI);
@ -741,9 +741,8 @@ bool LiveIntervals::tryFoldMemoryOperand(MachineInstr* &MI,
unsigned InstrIdx,
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
const TargetInstrDesc &TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
if (TID.isImplicitDef()) {
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();

1
llvm/lib/Target/Target.td
View File

@ -193,7 +193,6 @@ class Instruction {
bit isSimpleLoad = 0; // Is this just a load instruction?
bit mayLoad = 0; // Is it possible for this inst to read memory?
bit mayStore = 0; // Is it possible for this inst to write memory?
bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
bit isTwoAddress = 0; // Is this a two address instruction?
bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
bit isCommutable = 0; // Is this 3 operand instruction commutable?

1
llvm/utils/TableGen/CodeGenInstruction.cpp
View File

@ -86,7 +86,6 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isSimpleLoad = R->getValueAsBit("isSimpleLoad");
mayLoad = R->getValueAsBit("mayLoad");
mayStore = R->getValueAsBit("mayStore");
isImplicitDef= R->getValueAsBit("isImplicitDef");
bool isTwoAddress = R->getValueAsBit("isTwoAddress");
isPredicable = R->getValueAsBit("isPredicable");
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");

1
llvm/utils/TableGen/CodeGenInstruction.h
View File

@ -91,7 +91,6 @@ namespace llvm {
bool isCall;
bool isSimpleLoad;
bool mayLoad, mayStore;
bool isImplicitDef;
bool isPredicable;
bool isConvertibleToThreeAddress;
bool isCommutable;

1
llvm/utils/TableGen/InstrInfoEmitter.cpp
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@ -346,7 +346,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isSimpleLoad) OS << "|(1<<TID::SimpleLoad)";
if (mayLoad) OS << "|(1<<TID::MayLoad)";
if (mayStore) OS << "|(1<<TID::MayStore)";
if (Inst.isImplicitDef)OS << "|(1<<TID::ImplicitDef)";
if (Inst.isPredicable) OS << "|(1<<TID::Predicable)";
if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
if (Inst.isCommutable) OS << "|(1<<TID::Commutable)";