Remove the local register allocator.
Please use the fast allocator instead. llvm-svn: 106051
This commit is contained in:
Jakob Stoklund Olesen
parent
f267edd8ac
commit
ec2e964fd6
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@ -1594,22 +1594,22 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
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different register allocators:</p>
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<ul>
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<li><i>Simple</i> — This is a very simple implementation that does not
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keep values in registers across instructions. This register allocator
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immediately spills every value right after it is computed, and reloads all
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used operands from memory to temporary registers before each
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instruction.</li>
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<li><i>Local</i> — This register allocator is an improvement on the
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<i>Simple</i> implementation. It allocates registers on a basic block
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level, attempting to keep values in registers and reusing registers as
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appropriate.</li>
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<li><i>Linear Scan</i> — <i>The default allocator</i>. This is the
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well-know linear scan register allocator. Whereas the
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<i>Simple</i> and <i>Local</i> algorithms use a direct mapping
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implementation technique, the <i>Linear Scan</i> implementation
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uses a spiller in order to place load and stores.</li>
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<li><i>Fast</i> — This register allocator is the default for debug
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builds. It allocates registers on a basic block level, attempting to keep
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values in registers and reusing registers as appropriate.</li>
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<li><i>PBQP</i> — A Partitioned Boolean Quadratic Programming (PBQP)
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based register allocator. This allocator works by constructing a PBQP
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problem representing the register allocation problem under consideration,
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solving this using a PBQP solver, and mapping the solution back to a
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register assignment.</li>
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</ul>
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<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
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@ -1617,9 +1617,9 @@ bool RegMapping_Fer::compatible_class(MachineFunction &mf,
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<div class="doc_code">
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<pre>
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$ llc -regalloc=simple file.bc -o sp.s;
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$ llc -regalloc=local file.bc -o lc.s;
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$ llc -regalloc=linearscan file.bc -o ln.s;
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$ llc -regalloc=fast file.bc -o fa.s;
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$ llc -regalloc=pbqp file.bc -o pbqp.s;
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</pre>
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</div>
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@ -33,7 +33,6 @@ namespace {
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(void) llvm::createDeadMachineInstructionElimPass();
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(void) llvm::createLocalRegisterAllocator();
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(void) llvm::createFastRegisterAllocator();
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(void) llvm::createLinearScanRegisterAllocator();
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(void) llvm::createPBQPRegisterAllocator();
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@ -90,12 +90,6 @@ namespace llvm {
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///
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FunctionPass *createRegisterAllocator(CodeGenOpt::Level OptLevel);
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/// LocalRegisterAllocation Pass - This pass register allocates the input code
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/// a basic block at a time, yielding code better than the simple register
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/// allocator, but not as good as a global allocator.
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///
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FunctionPass *createLocalRegisterAllocator();
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/// FastRegisterAllocation Pass - This pass register allocates as fast as
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/// possible. It is best suited for debug code where live ranges are short.
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///
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@ -52,7 +52,6 @@ add_llvm_library(LLVMCodeGen
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PseudoSourceValue.cpp
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RegAllocFast.cpp
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RegAllocLinearScan.cpp
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RegAllocLocal.cpp
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RegAllocPBQP.cpp
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RegisterCoalescer.cpp
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RegisterScavenging.cpp
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File diff suppressed because it is too large
Load Diff
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=local
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; RUN: llc < %s -mtriple=arm-linux-gnueabi -regalloc=fast
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; PR1925
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=local
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; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=fast
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; PR1925
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=local
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; RUN: llc < %s -mtriple=armv5-unknown-linux-gnueabi -O0 -regalloc=fast
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; PR4100
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@.str = external constant [30 x i8] ; <[30 x i8]*> [#uses=1]
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@ -1,4 +1,3 @@
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; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=local
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; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast
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; rdar://problem/7948106
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;; This test would spill %R4 before the call to zz, but it forgot to move the
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@ -1,4 +1,3 @@
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; RUN: llc < %s -regalloc=local
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; RUN: llc < %s -regalloc=fast
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%struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8 }
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@ -1,5 +1,4 @@
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; RUN: llc < %s | FileCheck %s
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; RUN: llc < %s -regalloc=local | FileCheck %s
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; RUN: llc < %s -regalloc=fast | FileCheck %s
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; The first argument of subfc must not be the same as any other register.
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
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; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic
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%struct.NSError = type opaque
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=local -relocation-model=pic
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; RUN: llc < %s -mtriple=powerpc64-apple-darwin9 -regalloc=fast -relocation-model=pic
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%struct.NSError = type opaque
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=local
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; RUN: llc < %s -mtriple=powerpc-apple-darwin -regalloc=fast
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define i32 @bork(i64 %foo, i64 %bar) {
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@ -1,4 +1,3 @@
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; RUN: llc < %s -march=ppc32 -regalloc=local -O0 -relocation-model=pic -o -
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; RUN: llc < %s -march=ppc32 -regalloc=fast -O0 -relocation-model=pic -o -
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; PR1638
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@ -1,4 +1,3 @@
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; RUN: llc < %s -regalloc=local -relocation-model=pic | FileCheck %s
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; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s
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target triple = "thumbv6-apple-darwin10"
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@ -1,4 +1,3 @@
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; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=local
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; RUN: llc < %s -march=x86 -mattr=+sse2 -regalloc=fast
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define void @SolveCubic(double %a, double %b, double %c, double %d, i32* %solutions, double* %x) {
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@ -1,4 +1,3 @@
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; RUN: llc < %s -regalloc=local -march=x86 -mattr=+mmx | grep esi
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; RUN: llc < %s -regalloc=fast -march=x86 -mattr=+mmx | grep esi
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; PR2082
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; Local register allocator was refusing to use ESI, EDI, and EBP so it ran out of
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@ -1,5 +1,4 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=local
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim -O0 -regalloc=fast
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; PR5534
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=local
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; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=fast
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@_ZTVN10Evaluation10GridOutputILi3EEE = external constant [5 x i32 (...)*] ; <[5 x i32 (...)*]*> [#uses=1]
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@ -1,5 +1,4 @@
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; RUN: llc < %s -march=x86 | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=local | FileCheck %s
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; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s
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; %0 must not be put in EAX or EDX.
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@ -1,5 +1,4 @@
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; RUN: llc < %s -march=x86 | grep "#%ebp %esi %edi 8(%edx) %eax (%ebx)"
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; RUN: llc < %s -march=x86 -regalloc=local | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
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; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%edi %ebp %edx 8(%ebx) %eax (%esi)"
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; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=local -disable-fp-elim
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; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim
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; rdar://6538384
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@ -1,4 +1,3 @@
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; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=local | not grep sil
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; RUN: llc < %s -mtriple=i386-apple-darwin -O0 -regalloc=fast | not grep sil
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; rdar://6787136
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@ -1,6 +1,4 @@
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; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -regalloc=local -relocation-model=pic > %t
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; RUN: grep {leal.*TLSGD.*___tls_get_addr} %t
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=local -relocation-model=pic > %t2
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; RUN: llc < %s -march=x86-64 -mtriple=x86_64-linux-gnu -regalloc=fast -relocation-model=pic > %t2
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; RUN: grep {leaq.*TLSGD.*__tls_get_addr} %t2
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; PR4004
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@ -1,4 +1,3 @@
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; RUN: llc < %s -O0 -regalloc=local -relocation-model=pic -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -O0 -regalloc=fast -relocation-model=pic -disable-fp-elim | FileCheck %s
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
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target triple = "i386-apple-darwin10.0.0"
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@ -1,4 +1,3 @@
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; RUN-XFAIL: llc < %s -O0 -regalloc=local | FileCheck %s
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; RUN: llc < %s -O0 -regalloc=fast | FileCheck %s
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; PR6520
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@ -1,4 +1,3 @@
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; RUN: llc -regalloc=local %s -o %t
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; RUN: llc -regalloc=fast %s -o %t
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; PR7066
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@ -1,4 +1,3 @@
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; RUN: llc %s -O0 -fast-isel -regalloc=local -o -
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; RUN: llc %s -O0 -fast-isel -regalloc=fast -o -
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; PR4767
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@ -1,4 +1,3 @@
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; RUN: llc < %s -O3 -regalloc=local -mtriple=x86_64-apple-darwin10
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; RUN: llc < %s -O3 -regalloc=fast -mtriple=x86_64-apple-darwin10
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; <rdar://problem/7755473>
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@ -1,31 +0,0 @@
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; RUN: llc < %s -march=x86 -regalloc=local | grep {subl %eax, %edx}
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; Local regalloc shouldn't assume that both the uses of the
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; sub instruction are kills, because one of them is tied
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; to an output. Previously, it was allocating both inputs
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; in the same register.
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define i32 @func_3() nounwind {
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entry:
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%retval = alloca i32 ; <i32*> [#uses=2]
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%g_323 = alloca i8 ; <i8*> [#uses=2]
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%p_5 = alloca i64, align 8 ; <i64*> [#uses=2]
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%0 = alloca i32 ; <i32*> [#uses=2]
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%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
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store i64 0, i64* %p_5, align 8
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store i8 1, i8* %g_323, align 1
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%1 = load i8* %g_323, align 1 ; <i8> [#uses=1]
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%2 = sext i8 %1 to i64 ; <i64> [#uses=1]
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%3 = load i64* %p_5, align 8 ; <i64> [#uses=1]
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%4 = sub i64 %3, %2 ; <i64> [#uses=1]
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%5 = icmp sge i64 %4, 0 ; <i1> [#uses=1]
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%6 = zext i1 %5 to i32 ; <i32> [#uses=1]
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store i32 %6, i32* %0, align 4
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%7 = load i32* %0, align 4 ; <i32> [#uses=1]
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store i32 %7, i32* %retval, align 4
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br label %return
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return: ; preds = %entry
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%retval1 = load i32* %retval ; <i32> [#uses=1]
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ret i32 %retval1
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}
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@ -1,5 +1,5 @@
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; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
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; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=local | FileCheck %s
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; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
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; RUN: llc -O0 < %s -march=x86 -mtriple=i386-apple-darwin9 -regalloc=fast | FileCheck %s
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; CHECKed instructions should be the same with or without -O0.
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@.str = private constant [12 x i8] c"x + y = %i\0A\00", align 1 ; <[12 x i8]*> [#uses=1]
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